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EP0234907A2
Expired / Lapsed
EP
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Semiconductor memory device with redundant memory cell
Assignee: Fujitsu Ltd
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Filing: 1987-02-24
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Granted: —
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Expires: 2007-02-24
Abstract
Abstract A semiconductor memory device having a redundant memory cell array (12) by means of which faulty memory cells are replaced with redundant memory cells during the production process. The device comprises a forced release circuit (31,32) for releasing or cancelling the replacement of the faulty cells with the redundant memory cells, for example, by applying a voltage different from a normal voltage to one terminal of the device. This is useful for enabling the faulty states, and the causes of the faults, of the device to be determined.
Inventors
- 👤 Atsushi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 10:15
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
200 words
A semiconductor memory device, comprising: a plurality of memory cells; a decoder, connected to said memory cells, for selecting the memory cell corresponding to an accessing address; a redundant memory cell for replacing a faulty memory cell of the memory cells; a redundant decoder, connected to said redundant memory cell, for selecting the redundant memory cell; a first nonvolatile memory for memorizing an address of the faulty memory cell; a second nonvolatile memory for memorizing information indicating the use or nonuse of the redundant memory cell; a comparator means, connected to said first nonvolatile memory, for comparing the accessing address with the address of the faulty memory cell stored in the first nonvolatile memory and for making the redundant decoder active and making the decoder inactive when the accessing address coincides with the address of the faulty memory cell; and a forced release circuit connected to said comparator means, operable to release the replacement of the faulty memory cell by the redundant memory cell, to make the decoder active, and to make the redundant decoder inactive, in response to application of a forced redundant release signal, even when the accessing address coincides with the address of the faulty memory cell.
Claim 2
Dependent Claim
200 words
A semiconductor memory device, comprising: a plurality of memory cells; a decoder, connected to said memory cells, for selecting the memory cell corresponding to an accessing address; a redundant memory cell for replacing a faulty memory cell of the memory cells; a redundant decoder, connected to said redundant memory cell, for selecting the redundant memory cell; a first nonvolatile memory for memorizing an address of the faulty memory cell; a second nonvolatile memory for memorizing information indicating the use or nonuse of the redundant memory cell; a comparator means, connected to said first nonvolatile memory, for comparing the accessing address with the address of the faulty memory cell stored in the first nonvolatile memory and for making the redundant decoder active and making the decoder inactive when the accessing address coincides with the address of the faulty memory cell; and a forced release circuit connected to said comparator means, operable to release the replacement of the faulty memory cell by the redundant memory cell, to make the decoder active, and to make the redundant decoder inactive, in response to application of a forced redundant release signal, even when the accessing address coincides with the address of the faulty memory cell.
Claim 3
Dependent Claim
39 words
A semiconductor memory device as set forth in claim l, wherein said forced release circuit is connected to an output of the second nonvolatile memory,and wherein an output of said forced release circuit is connected to the comparator means.
Claim 4
Dependent Claim
41 words
A semiconductor memory device as set forth in claim l, wherein said forced release circuit is connected to the output of the comparator means,and wherein the output of said forced release circuit is connected to the decoder and the redundant decoder.
Claim 5
Dependent Claim
82 words
A semiconductor memory device as set forth in claim 2, wherein said forced release circuit is constituted by an inverter and a NOR gate,and wherein the output of the second nonvolatile memory is connected to the input of the inverter, the output of the inverter is connected to one input of the NOR gate, the forced redundant release signal is connected to the other input of the NOR gate, and the output of the NOR gate is connected to the comparator means.
Claim 6
Dependent Claim
84 words
A semiconductor memory device as set forth in claim 3, wherein said forced release circuit is constituted by an inverter and a NOR gate and the output of the comparator means is connected to the input of the inverter, the output of the inverter is connected to one input of the NOR gate, the forced redundant release signal is connected to the other input of the NOR gate, and the output of the NOR gate is connected to the decoder and the redundant decoder.
Claim 7
Dependent Claim
36 words
A semiconductor memory device as set forth in any preceding claim, wherein said forced redundant release signal is obtained by applying a voltage different from a normal voltage to one terminal of said semiconductor memory device.
References Cited (Backward Citations)
No citation records indexed.
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