Patent JPH02197136A successfully refreshed from Google Patents.
Patent EP0234891A2 successfully refreshed from Google Patents.
EP0234891A2
Expired / Lapsed
EP
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Semiconductor memory devices
Assignee: Fujitsu Ltd
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Filing: 1987-02-20
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Granted: —
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Expires: 2007-02-20
Abstract
Abstract A semiconductor memory device comprises a semiconductor substrate (1) of one conductivity type (p); a transistor (Tr) formed on the said substrate (1) and having a portion (92) serving as a source or drain, which portion is of the opposite conductivity type (n); and a storage capacitor (SC), comprising a first relatively conductive member consisting of a layer (5) provided on an inner surface region of a recess (4), formed in the said substrate (1), a dielectric layer (6) covering the said first conductive member (5) in the recess, and a second relatively conductive member (7) filling a remaining portion of the recess (4), so as to be surrounded by the said dielectric layer (6); there being an electrical connection between the said second conductive member (7) and the said portion (92) of the transistor (Tr). Such a memory device can reduce the occurrence of punch-through between adjacent storage (trench) capacitors and can reduce the possibility of soft errors.
Inventors
- 👤 Masao Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 20:49
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A semiconductor memory device comprising: a semiconductor substrate. (1) of one conductivity type (p); a transistor (Tr) formed on the said substrate (1) and having a portion (92) serving as a source or drain, which portion is of the opposite conductivity type (n); and a storage capacitor (SC), comprising a first relatively conductive member consisting of a layer (5) provided on an inner surface region of a recess (4), formed in the said substrate (1), a dielectric layer (6) covering the said first conductive member (5) in the recess, and a second relatively conductive member (7) filling a remaining portion of the recess (4), so as to be surrounded by the said dielectric layer (6); there being an electrical connection between the said second conductive member (7) and the said portion (92) of the transistor (Tr).
Claim 2
Dependent Claim
136 words
A semiconductor memory device comprising: a semiconductor substrate. (1) of one conductivity type (p); a transistor (Tr) formed on the said substrate (1) and having a portion (92) serving as a source or drain, which portion is of the opposite conductivity type (n); and a storage capacitor (SC), comprising a first relatively conductive member consisting of a layer (5) provided on an inner surface region of a recess (4), formed in the said substrate (1), a dielectric layer (6) covering the said first conductive member (5) in the recess, and a second relatively conductive member (7) filling a remaining portion of the recess (4), so as to be surrounded by the said dielectric layer (6); there being an electrical connection between the said second conductive member (7) and the said portion (92) of the transistor (Tr).
Claim 3
Dependent Claim
128 words
A dynamic random access memory having a trench capacitor, said memory comprising: a semiconductor substrate of one conduction type; a trench formed in said semiconductor substrate; a first conductive layer formed on the inner surface of said trench except for a region adjacent to the opening portion of said trench; a dielectric layer formed on said first conductive layer exposed in said trench and the surface of said semiconductor substrate; a second conductive layer filled in said trench through said dielectric layer; said first conductive layer, said dielectric layer, and said second conductive layer constituting a storage capacitor; and a metal insulator semiconductor transistor formed in said semiconductor substrate, having a source or drain region of the other conduction type which is connected to said second conductive layer.
Claim 4
Dependent Claim
128 words
A dynamic random access memory having a trench capacitor, said memory comprising: a semiconductor substrate of one conduction type; a trench formed in said semiconductor substrate; a first conductive layer formed on the inner surface of said trench except for a region adjacent to the opening portion of said trench; a dielectric layer formed on said first conductive layer exposed in said trench and the surface of said semiconductor substrate; a second conductive layer filled in said trench through said dielectric layer; said first conductive layer, said dielectric layer, and said second conductive layer constituting a storage capacitor; and a metal insulator semiconductor transistor formed in said semiconductor substrate, having a source or drain region of the other conduction type which is connected to said second conductive layer.
Claim 5
Dependent Claim
30 words
A memory according to claim 2, wherein said second conductive layer is electrically connected with said source or drain region of the other conduction type through a third conductive layer.
Claim 6
Dependent Claim
34 words
A memory according to claim 2 or 3, wherein a predetermined interval is formed between the upper end portion of said first conductive layer and the bottom level of said source or drain layer.
Claim 7
Dependent Claim
16 words
A memory according to claim 4, wherein said predetermined interval is occupied by an insulator material.
Claim 8
Dependent Claim
24 words
A memory according to claim 2, wherein said source or drain region is in adjacent to said second conductive layer through said dielectric layer.
Claim 9
Dependent Claim
21 words
A memory according to claim 2, wherein said first conductive layer is in contact with said semiconductor substrate in said trench.
Claim 10
Dependent Claim
15 words
A memory according to claim 2, wherein said first conductive layer comprises a polycrystalline silicon.
Claim 11
Dependent Claim
28 words
A memory according to claim 2, wherein said dielectric layer has a larger thickness at said surface of said semiconductor substrate than that on said first conductive layer.
References Cited (Backward Citations)
No citation records indexed.
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