Programmably controlled shifting mechanism in a programmable unit having variable data path widths

Claim 2

In a data processor having a storage location means to receive code specifying a shifting operation including the amount of bits that a data segment is to be shifted, said storage location also receiving a code specifying the width of the data segment to be shifted, a shifting mechanism comprising: a data bus having a width of M bits; shifting means coupled to said data bus to receive a data segment having a width of N bits where M is some multiple of N, said shifting means being coupled to said storage location to receive a shift amount value and to shift said data segment by the amount specified by said storage location; and input logic means coupled between said data bus and said shifting means and to said storage location means to receive said data segment of N bits for transfer to said shifting means.

Claim 3

A shifting mechanism according to Claim 1 wherein: said input logic means includes M logic gates coupled to said data bus, said logic gates being conditioned by said code specifying said data segment width to pass N bits of a received data segment and to block passage of M-N bit segments on said data bus.

Claim 4

A shifting mechanism according to claim 2 wherein: said shifting means includes multiplexor means coupled to said storage location means to receive a portion of said shift amount value, said multiplexor means being coupled to said input logic gates to receive said N bits of active data and said M-N bits which are all zero.

Claim 5

A shifting mechanism according to Claim 3 further including: shift control logic means coupled to said storage location means to receive said width of a data segment to be received, said shift control logic controlling the shifting of said data segment according to said shift amount value and said data segment width specification.

Claim 6

A shifting mechanism according to Claim 4 further including: output logic means coupled to said multiplexor means to receive said data segment as shifted in accordance with said shift amount value.

Claim 7

In a data processor having a storage location to receive code specifying a shifting operation including the amount of bits that a data segment is to be shifted and a second storage location to receive a code specifying the width of the data segment to be shifted, a shifting mechanism comprising: a data bus having a width of M bits: shifting means coupled to said data bus to receive a data segment having a width of N bits where M is some multiple of N including 1, said shifting means being coupled to said a storage location to receive a shift amount value and to shift said data segment by the amount specified by said a storage location; and input logic means coupled between said data bus and said shifting means to receive two sets of the bits of said data segment, one set for a right-hand shift and the other set for a left-hand shift with one or both sets of bits of said data segment being transferred to said shifting means.

Claim 8

In a data processor having a storage location to receive code specifying a shifting operation including the amount of bits that a data segment is to be shifted and a second storage location to receive a code specifying the width of the data segment to be shifted, a shifting mechanism comprising: a data bus having a width of M bits: shifting means coupled to said data bus to receive a data segment having a width of N bits where M is some multiple of N including 1, said shifting means being coupled to said a storage location to receive a shift amount value and to shift said data segment by the amount specified by said a storage location; and input logic means coupled between said data bus and said shifting means to receive two sets of the bits of said data segment, one set for a right-hand shift and the other set for a left-hand shift with one or both sets of bits of said data segment being transferred to said shifting means.

Claim 9

A shifting mechanism according to Claim 6 wherein: said input logic means includes two sets of M logic gates coupled to said data bus, said logic gates being conditioned by said code specifying said data segment width to pass only N bits of one or both received data segments and to block passage of the remaining bits in each of said data segments to said shifting means.

Claim 10

A shifting mechanism according to claim 7 wherein: said shifting means includes multiplexor means coupled to said a storage location to receive a portion of said shift amount value, said multiplexor means being coupled to said input logic gates to receive one or both sets of said N bits of active data with the remaining bits of each set being zero.

Claim 11

A shifting mechanism according to claim 7 further including: shifting control logic means coupled to said second storage location to receive said width of a data segment to be received, said shift control logic means controlling the shifting of said data segment according to said shift amount value and said data segment width specification.

Claim 12

A shifting mechanism according to Claim 9 further including: output means coupled to different sets of said multiplexor means to OR together different sets of said data segment as shifted when N is less than M.