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Patent EP0233734A2 successfully refreshed from Google Patents.
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EP0233734A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Clock signal generating circuit

Assignee: Fujitsu Ltd
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Filing: 1987-02-05
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Granted: —
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Expires: 2007-02-05
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Abstract

Abstract In a clock signal generating circuit for a semi­conductor large scale integrated circuit, the clock signal generating circuit includes: a P-channel transistor (Q₁) and a first N-channel transistor (Q₄), each connected in series between a positive side power source line (V CC ) and a ground side power source line (V SS ); a second N-channel transistor (Q₃) connected between a common connection point of the P-channel transistor and the first N-channel transistor and a gate of the first N-channel transistor through a node, and a clock signal (φ₁) is applied to a gate of the second N-channel transistor. A capacitor (C₁) is connected between the gate of the first N-channel transistor and a gate of the P-channel transistor; and a bootstrap capacitor (C) is connected to the common connection point. Such a clock signal generating circuit can provide clock signals with improved speed, precision and reliability as compared with those generated by prior art clock signal generating circuits.

Inventors

  • 👤 Yoshihiro Takemae

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 16:11
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/12; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735; H03K17/00; H03K17/04

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 111 words
A clock signal generating circuit for a semiconductor large scale integrated circuit comprising: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a second N-channel transistor connected between a common connection point of said P-channel transistor and said first N-channel transistor and a gate of said first N-channel transistor through a node, and a clock signal being applied to a gate of said second N-channel transistor; a capacitor connected between said gate of said first N-channel transistor and a gate of said P-channel transistor; and a bootstrap capacitor connected to said common connection point.
Claim 2
Dependent Claim 111 words
A clock signal generating circuit for a semiconductor large scale integrated circuit comprising: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a second N-channel transistor connected between a common connection point of said P-channel transistor and said first N-channel transistor and a gate of said first N-channel transistor through a node, and a clock signal being applied to a gate of said second N-channel transistor; a capacitor connected between said gate of said first N-channel transistor and a gate of said P-channel transistor; and a bootstrap capacitor connected to said common connection point.
Claim 3
Dependent Claim 95 words
A clock signal generating circuit for a semiconductor large scale integrated circuit comprising: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a second node, and each having a complementary relationship; a second N-channel transistor connected between said second node and a ground side power source line; a third N-channel transistor connected between said second node and a gate of said second N-channel transistor through a first node; a capacitor connected to said first node; and a bootstrap capacitor connected to said second node.
Claim 4
Dependent Claim 95 words
A clock signal generating circuit for a semiconductor large scale integrated circuit comprising: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a second node, and each having a complementary relationship; a second N-channel transistor connected between said second node and a ground side power source line; a third N-channel transistor connected between said second node and a gate of said second N-channel transistor through a first node; a capacitor connected to said first node; and a bootstrap capacitor connected to said second node.

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