A time delay circuit for a semiconductor device

Abstract

Abstract A plurality of time delay circuits (1-1, 1-2,...), usually a dummy word line made similarly to a word line having a delay characteristics for charging and discharging, are provided in a memory device in place of a single delay circuit of prior art. A selection circuit (11) selectively drives one of the delay circuits (1-1, 1-2,...) and enables a gate connected to the driven delay circuit (1-1, 1-2,...) in a circulating sequence each time an input pulse is received. A gate circuit 12 detects a moment at which the output voltage of the dummy word line reaches a threshold level and then outputs an enabling signal to the readout sense amplifier. A noise coming-in closely before a normal signal is led to a delay circuit (1-1, 1-2,...) but disabled by the normal signal, thus having no effect on the signal. So, the invention is effective when the input signal is from an address transition detector (10) which, used in an asynchronous memory device, is apt to produce the above-described type of noise. And further, immediately after an enabling signal is outputted, a next address change is acceptable, because the next delay circuit is ready to function without being disturbed by the remaining voltage in the previously used delay circuit. Thus, both the increased speed of memory cycling and the increasedscale of integration can be achieved at the same time.

Inventors

• 👤 Atsushi Takeuchi

Bibliographic Details