Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
181 words
A vector processor comprising a main storage (10) which has a plurality of banks (B O ...B 3 ) ' storage control circuits (9, 11) which control store and fetch of said main storage (10), a plurality of vector registers (3), a plurality of memory requesters (6, 7) which transfer data between said vector registers (3) and said main storage (10), and a plurality of vector arithmetic units which subject vector data received from said vector registers (3) to vector operations and which send operated results to said vector registers; each said memory requester (6, 7) including stacks which store a main storage access request; each said storage control circuit (9, 11) for said main storage (10) including a comparator circuit (77) which compares addresses in said main storage (10) between vector elements for the main storage access requests, and a logic circuit (78, 79, 81, 82) which cancels a main storage access that becomes invalid when the addresses in said main storage (10) between the adjacent vector elements have agreed as a result of the comparison in said comparator circuit.
Claim 2
Dependent Claim
181 words
A vector processor comprising a main storage (10) which has a plurality of banks (B O ...B 3 ) ' storage control circuits (9, 11) which control store and fetch of said main storage (10), a plurality of vector registers (3), a plurality of memory requesters (6, 7) which transfer data between said vector registers (3) and said main storage (10), and a plurality of vector arithmetic units which subject vector data received from said vector registers (3) to vector operations and which send operated results to said vector registers; each said memory requester (6, 7) including stacks which store a main storage access request; each said storage control circuit (9, 11) for said main storage (10) including a comparator circuit (77) which compares addresses in said main storage (10) between vector elements for the main storage access requests, and a logic circuit (78, 79, 81, 82) which cancels a main storage access that becomes invalid when the addresses in said main storage (10) between the adjacent vector elements have agreed as a result of the comparison in said comparator circuit.
Claim 3
Dependent Claim
50 words
The vector processor of claim 1, wherein said logic circuit (78, 79, 81, 82) is a circuit which processes the succeeding main storage access request as a dummy request when, in a vector load mode, the addresses have agreed as the result of the comparison by said comparator circuit (77).
Claim 4
Dependent Claim
52 words
The vectcr processor of claim 1, wherein said logic circuit (78, 79, 81, 82) is a circuit which cancels the preceding main storage access request within said memory requester (6, 7) when, in a vector store mode, the addresses have agreed as the result of the comparison by said comparator circuit (77).
Claim 5
Dependent Claim
109 words
The vector processor of any of claims 1 to 3, wherein said main storage (10) is constructed on n banks, said vector registers (3) are comprised in a number m, and said memory requesters (6, 7) and said vector arithmetic units are respectively comprised in a number t (n ≠ m ≠ ℓ); logic circuit groups which have three sorts of block structures are provided for the above three sorts of resources; and in transmitting'a signal from the i-th block to the j (≠i)-th block, a conversion process is performed by a switching circuit (211...213), thereby to determine the combination of the numbers n, m and t at will.
Claim 6
Dependent Claim
182 words
The vector processor of any of claims 1 to 4, wherein said storage control circuit comprises means to affix a tag indicative of validity or invalidity to the main storage access request in order to regard the succeeding main storage access request of the agreeing addresses as a dummy request in case of a vector load process; means to replace the address with a random number in case of the invalid request, thereby to transform the main storage access requests into main storage access request train in which no bank conflict arises between the adjacent vector elements; and means to put information held on the tag, into a set signal of a latch circuit constituting a register installed in a control circuit for performing a process in which data fetched from a RAM constructing each said bank of said main storage is written into said vector register, and to store only the vector data fetched from the bank in compliance with the valid main storage access request, in said vector register by means of a control circuit for controlling the set signal.