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EP0232038A2
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EP
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Semiconductor integrated circuit with detection circuit for address signal change
Assignee: Fujitsu Ltd
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Filing: 1987-01-19
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Granted: —
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Expires: 2007-01-19
Abstract
Abstract A semiconductor integrated circuit with a detection circuit for detecting an address signal change comprises a plurality of gate circuits (21, 22. 23), and a plurality of resettable delay circuits (24. 25). Each delay circuit (24. 25) is reset when an address signal (A) or an inverted address signal ( ) is at a predetermined polarity and level. Thus the circuit generates a pulse having a pulse width no shorter than a predetermined time interval upon each address change even if that change is only caused by noise.
Inventors
- 👤 Atsushi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/13; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
184 words
A semiconductor integrated circuit includ- in g a detection circuit for detecting a change of an input signal comprising: a first gate circuit (21, 41) for receiving an input signal (A) at one of its inputs; a second gate circuit_(22, 42) for receiving an inverted input signal (A) at one of its inputs; a third gate circuit (23, 43) for receiving outputs of the first gate circuit (21, 41) and second gate circuit (22,42); a first delay circuit (24, 44) receiving an output of the second gate circuit (22, 42), and delaying the output of the second gate circuit (22, 42) for a predetermined time interval, an output of the second delay circuit (25. 45) being connected to another input of the second gate circuit (22, 42); characterised in that the first and second delay circuits (24, 44 and 25, 45) are both resettable delay circuits; the first resettable delay circuit (24, 44) being reset in response to a change of the input signal (A); and, the second resettable delay circuit (25,45) being reset in response to a change of the inverted input signal.
Claim 2
Dependent Claim
184 words
A semiconductor integrated circuit includ- in g a detection circuit for detecting a change of an input signal comprising: a first gate circuit (21, 41) for receiving an input signal (A) at one of its inputs; a second gate circuit_(22, 42) for receiving an inverted input signal (A) at one of its inputs; a third gate circuit (23, 43) for receiving outputs of the first gate circuit (21, 41) and second gate circuit (22,42); a first delay circuit (24, 44) receiving an output of the second gate circuit (22, 42), and delaying the output of the second gate circuit (22, 42) for a predetermined time interval, an output of the second delay circuit (25. 45) being connected to another input of the second gate circuit (22, 42); characterised in that the first and second delay circuits (24, 44 and 25, 45) are both resettable delay circuits; the first resettable delay circuit (24, 44) being reset in response to a change of the input signal (A); and, the second resettable delay circuit (25,45) being reset in response to a change of the inverted input signal.
Claim 3
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 1, wherein the first (21), second (22), and third (23) gate circuits are NAND gates.
Claim 4
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 1, wherein the first (41), second (42), and third (43) gate circuits are NOR gates.
Claim 5
Dependent Claim
227 words
A semiconductor integrated circuit according to any one of the preceding claims, wherein each resettable delay circuit (24, 25, 44, 45) comprises a capacitor (C1), a resistance (R1), first (Q1), second (Q2), third (Q4), and fourth (Q5) transistors, and an inverter (Q3, Q6); the capacitor (C1) being charged to a high level through the first transistor (Q1) when the first transistor receives at its gate a low level signal from the input signal (A) or the inverted input signal (A); the capacitor (C1) being charged to a high level through the second transistor (Q2) when the second transistor (Q2) receives at its gate a low level signal (C', d') from an output of a gate circuit (22, 21) connected to an output of the other resettable delay circuit (25,24); an electric charge in the capacitor (C1) being discharged through the third transistor (Q4), the fourth transistor (Q5), and the resistance (R1) when the third transistor (Q4) receives at its gate a high level signal from the input signal (A) or the inverted input signal (A), and when the fourth transistor (Q5) receives at its gate a high level signal (c', d') from the output of the said gate circuit (22,21); and, a voltage across the capacitor (C1) being amplified and inverted by a predetermined threshold through the inverter (Q3, Q6) and supplied as an output (e', f').
References Cited (Backward Citations)
No citation records indexed.
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