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EP0231574A2
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Cache-based computer systems
Assignee: MIPS Computer Systems Inc
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Filing: 1986-07-11
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Granted: —
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Expires: 2006-07-11
Abstract
Abstract A cache-based computer architecture in which an address generating unit (12) and a tag comparator (14) are packaged together and separately from cache RAMs (26,28). If the architecture supports virtual memory, an address translation unit (50) may be included on the same chip (10) as, and logically between, the address generating unit and the tag comparator (14) logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses (22,16,24).
Inventors
- 👤 John P. Moussouris
- 👤 Lester M. Crudele
- 👤 Steven A. Przybylski
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:09
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
178 words
A computer system comprising: a package (10) containing an address generating unit (12) and a tag comparator (14); a first set (26, 28) of cache memory comprising a first cache data memory (28) and a first cache tag memory (26); data bus means (16) in communication with the first cache data memory (28); tag bus means (24) in communication with the tag comparator (14) and the first cache tag memory (26); address bus means (22,54) comprising a first group (54) of m address leads and a second group (22) of n address leads, the first group (54) of address leads being in communication with the tag comparator (14) and the second group (22) of address leads being in communication with the first cache tag memory (26) and the first cache data memory (28); and first connection means (18;50;52) for placing the first group (54) of address leads and the second group (22) of address leads in communication with the address generating unit (12); wherein the first set of cache memory (26,28) is disposed externally to the package (10).
Claim 2
Dependent Claim
178 words
A computer system comprising: a package (10) containing an address generating unit (12) and a tag comparator (14); a first set (26, 28) of cache memory comprising a first cache data memory (28) and a first cache tag memory (26); data bus means (16) in communication with the first cache data memory (28); tag bus means (24) in communication with the tag comparator (14) and the first cache tag memory (26); address bus means (22,54) comprising a first group (54) of m address leads and a second group (22) of n address leads, the first group (54) of address leads being in communication with the tag comparator (14) and the second group (22) of address leads being in communication with the first cache tag memory (26) and the first cache data memory (28); and first connection means (18;50;52) for placing the first group (54) of address leads and the second group (22) of address leads in communication with the address generating unit (12); wherein the first set of cache memory (26,28) is disposed externally to the package (10).
Claim 3
Dependent Claim
75 words
A computer system according to claim 1, wherein the first connection means comprises: virtual address bus means (52) in communication with the address generating unit (12); an address translation unit (50) disposed inside the package (10) and in communication with the virtual address bus means (52); and second connection means for placing the first group (54) of address leads and the second group (22) of address leads in communication with the address translation unit (50).
Claim 4
Dependent Claim
114 words
A computer system according to claim 1 or claim 2, further comprising a second set (82,84) of cache memory comprising a second cache data memory and a second cache tag memory, the second cache data memory being in communication with the second group (22) of address leads and with the data bus means (16) and the second cache tag memory being in communication with the second group (22) of address leads and with the tag bus means (24), wherein the second set of cache memory is disposed externally to the package (10), and wherein access to the second set (82,84) of cache memory is interleaved with access to the first set of cache memory.
Claim 5
Dependent Claim
68 words
A computer system according to claim 1, claim 2 or claim 3, further comprising: means for enabling information from the first cache tag memory (26) onto the tag bus means (24) at a first predetermined point in time; and means for enabling information from the first cache data memory (28) onto the data bus means (16) at substantially the same time as the first predetermined point in time.
Claim 6
Dependent Claim
54 words
A computer system according to claim 2, or claim 3 or claim 4 when dependent on claim 2, wherein at least one lead in the second group (22) of address leads represents a translated address bit and at least one lead in the second group (22) of address leads represents an untranslated address bit.
Claim 7
Dependent Claim
66 words
A computer system according to claim 2, or any one of claims 3 to 5 when dependent on claim 2, wherein the address translation unit (50) is operable to translate j leads and leaves k leads unaltered, the virtual address bus means (52) comprising j + k leads, and wherein: n is greater than k; and the first set (26,28) of cache memory is direct mapped.
References Cited (Backward Citations)
No citation records indexed.
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