Microcomputer having a highspeed operation mode and a low-speed operation mode

Claim 2

A microcomputer having a high-speed operation mode and a low-speed operation mode comprising a memory storing a plurality of instructions, a reading circuit coupled to said memory and reading an instruction out of said memory, and a control circuit coupled to said reading circuit and applying a first enable signal in the high-speed operation mode and a second enable signal in the low-speed operation mode to said reading circuit, said reading circuit being activated during a full time in said high-speed operation mode by said first enable signal and being activated intermittently in said low-speed operation mode by said second enable signal.

Claim 3

A microcomputer as claimed in claim 1, wherein said reading circuit has a current mirror type sense amplifier which has a switching circuit to couple a bit line of said memory to a current mirror circuit of said reading circuit, said switching circuit being turned on during a full time of the high-speed operation mode by said first enable signal and being intermittently turned on in the low-speed operation mode by said second enable signal.

Claim 4

a microcomputer as claimed in claim 1, wherein said control circuit receives a mode designating signal and a reading control signal with a predetermined duty rate and generates said first enable signal which is activated regardless of said reading control signal when said mode designating signal is a first level designating the high-speed operation mode and generates said second enable signal which is activated according said read control signal when said mode designating signal is a second level designating the low-speed operation mode.

Claim 5

A microcomputer comprising a memory having a plurality of bit lines and a dummy line, a first current mirror type sense amplifier connected to one of said plurality of bit lines through a first switching circuit, a second current mirror type sense amplifier connected to said dummy line through a second switching circuit, an output of said second current mirror type sense amplifier being applied as a reference signal to said first current mirror type sense amplifier, an output of said memory being derived from said first current mirror type sense amplifier, a first means for selectively generating a first enable signal which is always activated in a high-speed operation mode and a second enable signal which is intermittently activated in a low-speed operation mode, and a second means coupled between said first means and said first and second switching circuits for controlling said first and second switching circuits according to said first and second enable signals.

Claim 6

A microcomputer comprising a memory having a plurality of bit lines and a dummy line, a first current mirror type sense amplifier connected to one of said plurality of bit lines through a first switching circuit, a second current mirror type sense amplifier connected to said dummy line through a second switching circuit, an output of said second current mirror type sense amplifier being applied as a reference signal to said first current mirror type sense amplifier, an output of said memory being derived from said first current mirror type sense amplifier, a first means for selectively generating a first enable signal which is always activated in a high-speed operation mode and a second enable signal which is intermittently activated in a low-speed operation mode, and a second means coupled between said first means and said first and second switching circuits for controlling said first and second switching circuits according to said first and second enable signals.

Claim 7

A microcomputer as claimed in claim 4, wherein said first and second switching circuits are always turned on in response to said first enable signal and are intermittently turned on in response to said second enable signal.

Claim 8

A microcomputer comprising a memory storing instructions, a sense amplifier connected to said memory to read an instruction out of said memory, and a control circuit connected to said sense amplifier and activating said sense amplifier with a large duty rate when a high-speed operation mode is designated and activating said sense amplifier with a short duty rate when a low-speed operation mode is designated.

Claim 9

A microcomputer comprising a memory storing instructions, a sense amplifier connected to said memory to read an instruction out of said memory, and a control circuit connected to said sense amplifier and activating said sense amplifier with a large duty rate when a high-speed operation mode is designated and activating said sense amplifier with a short duty rate when a low-speed operation mode is designated.