CMOS encoder circuit

Claim 2

An encoder circuit comprising a) a plurality of input lines on each of which is to appear a logic "1" or "0" signal, b) a plurality of output lines, c) a first set of transistors of a first conductivity type, each of the first set transistors having a control terminal connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a second set of transistors of a second conductivity type opposite to said first conductivity type, each of the second set transistors having a control terminal connected to each of said input lines and input and output terminals between each of said output lines and a reference voltage source, and e) a plurality of logic inverter devices each connected between each of said input lines and each of the transistors of one of said first and second conductivity types.

Claim 3

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "0" signal bit, b) a plurality of output lines, c) a set of p-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a set of n-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a reference voltage source, and e) a plurality of logic inverter devices each connected between each of said input lines and each of the n-channel field-effect transistors.

Claim 4

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "0" signal bit, b) a plurality of output lines, c) a set of p-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a set of n-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a reference voltage source, and e) a plurality of logic inverter devices each connected between each of said input lines and each of the n-channel field-effect transistors.

Claim 5

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "1" signal bit, b) a plurality of output lines, c) a set of p-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a set of n-channel field-effect transistors each of which has a gate connected to each of said input lines and a source and a drain connected between each of said output lines and a reference voltage source, and e) a plurality of logic inverter devices each connected between each of said input lines and each of the p-channel field-effect transistors.

Claim 6

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "1" signal bit, b) a plurality of output lines, c) a set of p-channel field-effect transistors each of which has a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a set of n-channel field-effect transistors each of which has a gate connected to each of said input lines and a source and a drain connected between each of said output lines and a reference voltage source, and e) a plurality of logic inverter devices each connected between each of said input lines and each of the p-channel field-effect transistors.

Claim 7

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "0" signal bit, b) a plurality of output lines, c) a first transistor zone within which a first set of field-effect transistors of a first conductivity type are located, each of the first set field-effect transistors having a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a second transistor zone within which a second set of field-effect transistors of a second conductivity type opposite to said first conductivity type are located, each of the second set field-transistors having a gate connected to each of said input lines and a current path connected between each of said output lines and a reference voltage source, and e) an inverter zone within which a plurality of logic inverter devices are located, each of the logic inverters being connected between each of said input lines and each of the field-effect transistors of one of said first and second sets, f) said inverter zone intervening between said first and second transistor zones.

Claim 8

An encoder circuit comprising a) a plurality of input lines on which is to appear a signal consisting of bits including only one "0" signal bit, b) a plurality of output lines, c) a first transistor zone within which a first set of field-effect transistors of a first conductivity type are located, each of the first set field-effect transistors having a gate connected to each of said input lines and a current path connected between each of said output lines and a supply voltage source, d) a second transistor zone within which a second set of field-effect transistors of a second conductivity type opposite to said first conductivity type are located, each of the second set field-transistors having a gate connected to each of said input lines and a current path connected between each of said output lines and a reference voltage source, and e) an inverter zone within which a plurality of logic inverter devices are located, each of the logic inverters being connected between each of said input lines and each of the field-effect transistors of one of said first and second sets, f) said inverter zone intervening between said first and second transistor zones.

Claim 9

An encoder circuit as set forth in claim 4, in which said first set of field-effect transistors consist of p-channel field-effect transistors and said second set of field-effect transistors consist of n-channel field-effect transistors.

Claim 10

An encoder circuit as set forth in claim 4, in which said first set of field-effect transistors consist of n-channel field-effect transistors and said second set of field-effect transistors consist of p-channel field-effect transistors.