Encryption/decryption system

Claim 2

An encryption/decryption system for encrypting an input digital signal at a transmitting end of a communications channel and for reproducing the input signal at a receiving end of said channel, said system comprising: at the transmitting end: encrypted signal composing means for combining a randomized coding signal with the input digital signal to form an encrypted signal which is segmented into frames; first register means for storing a predetermined number of bits m of the encrypted signal output from the composing means and for outputting a plurality of the stored bits in parallel; first memory means for receiving the output from the first register means as an address input and for outputting a corre­sponding prestored n bit random number for each of the various input addresses, where n is an integer which is at least 2; and first selecting means for randomly selecting an output from among the n bit random number data output by the first memory means, to form a frame length of bits of the randomized coding signal; and at the receiving end: second register means for storing m bits of a received encrypted signal and outputting a plurality of the stored bits in parallel; second memory means for receiving the output from the second register means as an address input and for outputting a corre­sponding prestored n bit random number for each of the various input addresses, the stored contents of the first and second memory means being identical; second selecting means, operating the same way as the first selecting means, for selecting an output from among the random number data output by the second memory means, to provide a decoding signal by forming a frame of bits in sync with a corre­sponding frame of the encrypted signal; and digital signal reproducing means for combining the received encrypted signal with the decoding signal to reproduce the input digital signal.

Claim 3

The encryption/decryption system of claim l wherein the first selecting means has a first random number generator for generating a random number for each frame, and a first selector circuit controlled in accordance with the random number output of the first random number generator for selecting one output from among the n bit random number data output by the first memory means; and the second selecting means has a second random number generator for generating a random number for each frame in sync with a corresponding frame of the encrypted signal, and a second selec­tor circuit controlled in accordance with the random number output of the second random number generator for selecting one output from among the n bit random number data output by the second memory means.

Claim 4

An encryption/decryption system for encrypting an input digital signal at the transmitting end of a communications chan­nel and for reproducing the input signal at the receiving end, said system comprising: at the transmitting end: encrypted signal composing means for combining a randomized coding signal with the input digital signal to form an encrypted signal segmented into frames; first register means having storing contents comprising a predetermined number of bits m of the encrypted signal output from the composing means and for outputting a plurality of the stored bits in parallel; first selecting means for randomly selecting an output, for each signal frame, responsive to the m bit number data output by the first register means and for outputting corresponding n bit address numbers, where n is an integer which is at least 2; and first memory means for producing the bits of the randomized coding signal responsive to receiving the n bit addresses output from the first selecting means by outputting for each address a corresponding random bit which is prestored at the address; and at the receiving end: second register means for storing m bits of a received encrypted signal and for outputting a plurality of the stored bits in parallel; second selecting means, operating the same way as the first selecting means and in sync with a corresponding frame of the encrypted signal, for selecting an output responsive to the m bit number data output by the second register means and outputting corresponding n bit address numbers; second memory means, having stored contents which are iden­tical to the contents stored in the first memory means, said second memory means producing a prestored decoding signal respon­sive to receiving the n bit addresses output from the second selecting means, said second memory means outputting a corre­sponding random bit prestored at the corresponding address; and digital signal reproducing means for combining the received encrypted signal with the decoding signal to reproduce the input digital signal.

Claim 5

An encryption/decryption system for encrypting an input digital signal at the transmitting end of a communications chan­nel and for reproducing the input signal at the receiving end, said system comprising: at the transmitting end: encrypted signal composing means for combining a randomized coding signal with the input digital signal to form an encrypted signal segmented into frames; first register means having storing contents comprising a predetermined number of bits m of the encrypted signal output from the composing means and for outputting a plurality of the stored bits in parallel; first selecting means for randomly selecting an output, for each signal frame, responsive to the m bit number data output by the first register means and for outputting corresponding n bit address numbers, where n is an integer which is at least 2; and first memory means for producing the bits of the randomized coding signal responsive to receiving the n bit addresses output from the first selecting means by outputting for each address a corresponding random bit which is prestored at the address; and at the receiving end: second register means for storing m bits of a received encrypted signal and for outputting a plurality of the stored bits in parallel; second selecting means, operating the same way as the first selecting means and in sync with a corresponding frame of the encrypted signal, for selecting an output responsive to the m bit number data output by the second register means and outputting corresponding n bit address numbers; second memory means, having stored contents which are iden­tical to the contents stored in the first memory means, said second memory means producing a prestored decoding signal respon­sive to receiving the n bit addresses output from the second selecting means, said second memory means outputting a corre­sponding random bit prestored at the corresponding address; and digital signal reproducing means for combining the received encrypted signal with the decoding signal to reproduce the input digital signal.

Claim 6

The encryption/decryption system of claim 3 wherein the first selecting means has a first random number generator for generating a random number for each frame, and a first selector circuit controlled in accordance with the random number output of the first random number generator for selecting an output respon­sive to the output of the first register means; and the second selecting means has a second random number generator for generating a random number for each frame in sync with a corresponding frame of the encrypted signal, and a second selec­tor circuit controlled in accordance with the random number output of the second random number generator for selecting an output responsive to the outputs of the second register means.

Claim 7

An encryption/decryption system comprising means for storing a plurality of identical encryption/decryption keys at opposite ends of a communication channel, means for identifying each of said keys by an individually associated address, selector means responsive to the receipt of an information data word which is transmitted over said channel for selecting an address of a key which is used for encryption/decryption of that data word, means for combining said data word and the key which is stored at the selected address for encrypting/decrypting said data word, and means responsive to a transmission of said information data word for periodically incrementing said key address.

Claim 8

An encryption/decryption system comprising means for storing a plurality of identical encryption/decryption keys at opposite ends of a communication channel, means for identifying each of said keys by an individually associated address, selector means responsive to the receipt of an information data word which is transmitted over said channel for selecting an address of a key which is used for encryption/decryption of that data word, means for combining said data word and the key which is stored at the selected address for encrypting/decrypting said data word, and means responsive to a transmission of said information data word for periodically incrementing said key address.

Claim 9

The system of claim 5 and means for randomly changing said identical encryption/decryption keys stored at said opposite ends of said communication channel.

Claim 10

The system of claim 6 wherein said randomly changeable means comprises a randomly cross wired transmitter and receiver memory unit at said opposite ends of said communication channel.

Claim 11

The system of claim 6 wherein information data words are sent in frames, said address selector means comprises a shift register which is incremented responsive to each frame of data words, the output of said shift register indicating said address.

Claim 12

The system of claim 8 and encoder means, said shift register means being coupled to drive said random changing means, said random changing means being coupled to drive said encoder means, and said encoder means being coupled to drive said combining means.

Claim 13

l0. The system of claim 8 and decoder means, said shift register means being coupled to drive said random changing means, said random changing means being coupled to drive said decoder means, and decoder means being coupled to drive said combining means.

Claim 14

The system of claim 8 and encoder means, said shift register being coupled to drive said encoder means, said encoder means being coupled to drive said random changing means, and said random changing means being coupled to drive said combining means.

Claim 15

The system of claim 8 and decoder means, said shift register being coupled to drive said decoder means, said decoder means being coupled to drive said random changing means, and said random changing means being coupled to drive said combining means.