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EP0227128A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Memory device including a sense amplifier

Assignee: Toshiba Corp
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Filing: 1981-09-16
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Granted: —
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Expires: 2001-09-16
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Abstract

Abstract A memory device is disclosed having memory cells (6) for storing binary data, a data line (2) coupled to the memory cells for transferring data stored in the memory cells, a decoder (4) for selecting one of the memory cells to couple the selected memory cell (6) with the data line (2), the potential - (VS) of the data line being changed with the stored data of the selected memory cell, and a sense amplifier (10) coupled to the data line (2) for sensing the stored data of the slected memory cell (6) and providing a read out output (e) corresponding to the sensed stored data. The sense amplifier (10) includes a hysteresis comparator (R1, R2, R4, 470, 472) comprising a first transistor (470) whose gate receives the data line potential (VS), a second transistor (472) whose gate and source are respectively connected to the drain and source of the first transistor (470), and whose drain provides the read out output (e), a first resistor (R1) connected between the source of the first transistor (470) and a first power supply potential (GND), a second resistor - (R2) connected between the drain of the first transistor (470) and a second power supply potential (VD) and a third resistor (R3) connected between the drain of said second transistor (472) and the second power supply potential (VD), arranged so that a source potential (y) of the first transistor (470) represents two potentials, one of which depends on the resistance ratio of the first and second resistors (R1, R2) and corresponds to the first threshold level (VH) and the other of which depends on the resistance ratio of the first and third resistors (R1, R3) and correponds to the second threshold level (VL). F I G. 4

Inventors

  • 👤 Iwahashi Hiroshi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 22:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/065; G11C7/067

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 349 words
A memory device comprising: memory cells for storing given data; a data line coupled to said memory cells for transferring data stored in said memory cells; a decoder coupled to said memory cells for selecting one of said memory cells to electrically relate the selected memory cell with said data line, the potential of said data line being changed with the stored data of said selected memory cell; and a sense amplifier coupled to said data line for sensing the stored data of said selected memory cell and providing a read out output corresponding to the sensed stored data; said sense amplifier including; a sensor means responsive to a first threshold level and a second threshold level for providing said read out output such that, when the data line potential departs from the first threshold level said sensor means provides a read out output representing first stored data, and when the data line potential reaches the second threshold level, said sensor means provides a read out output representing a second stored data, characterised in that said sensor means (120 = 194) includes a first transistor (470) whose gate receives said data line potential (VS); a second transistor (472) whose gate and source are respectively connected to the drain and source of said first transistor (470), and whose drain provides said read out output (e); first impedance means (R1) connected between the source of said first transistor (470) and first power supply potential (GND); second impedance means (R2) connected between the drain of said first transistor (470) and a second power supply potential (VD);and third impedance means (R3) connected between the drain of said second transistor (472) and said second power supply potential (VD); in which a source potential (y) of said first transistor (470) represents two potentials, one of which depends on the resistance ratio of said first and second impedance means (R1, R2) and corresponds to said first threshold level (VH), and the other of which depends on the resistance ratio of said first and third impedance means (R1, R3) and corresponds to said second threshold level (VL).
Claim 2
Dependent Claim 349 words
A memory device comprising: memory cells for storing given data; a data line coupled to said memory cells for transferring data stored in said memory cells; a decoder coupled to said memory cells for selecting one of said memory cells to electrically relate the selected memory cell with said data line, the potential of said data line being changed with the stored data of said selected memory cell; and a sense amplifier coupled to said data line for sensing the stored data of said selected memory cell and providing a read out output corresponding to the sensed stored data; said sense amplifier including; a sensor means responsive to a first threshold level and a second threshold level for providing said read out output such that, when the data line potential departs from the first threshold level said sensor means provides a read out output representing first stored data, and when the data line potential reaches the second threshold level, said sensor means provides a read out output representing a second stored data, characterised in that said sensor means (120 = 194) includes a first transistor (470) whose gate receives said data line potential (VS); a second transistor (472) whose gate and source are respectively connected to the drain and source of said first transistor (470), and whose drain provides said read out output (e); first impedance means (R1) connected between the source of said first transistor (470) and first power supply potential (GND); second impedance means (R2) connected between the drain of said first transistor (470) and a second power supply potential (VD);and third impedance means (R3) connected between the drain of said second transistor (472) and said second power supply potential (VD); in which a source potential (y) of said first transistor (470) represents two potentials, one of which depends on the resistance ratio of said first and second impedance means (R1, R2) and corresponds to said first threshold level (VH), and the other of which depends on the resistance ratio of said first and third impedance means (R1, R3) and corresponds to said second threshold level (VL).
Claim 3
Dependent Claim 42 words
A memory device as claimed in claim 1 wherein said first threshold level (VH) corresponds to the maximum level of said data line potential - (VS), and said second threshold level (VL) to the minimum level of said data line potential (VS).

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