A method of manufacturing IGFETs having minimal junction depth using epitaxial recrystallization

Claim 1

A method of manufacturing an insulated gate field effect transistor (IGFET) within a predetermined area of a substrate (1) of monocrystalline silicon of a first conductivity type, comprising the steps of - forming a first insulating layer (10) in a first localized region of said predetermined area of the substrate (1), - forming a conductive layer (9) above said first insulating layer (10), - forming a second insulating layer (8) above said conductive layer (9), - wherein the first insulating layer (10) and the conductive layer (9) are intended to constitute the dielectric layer of the gate and the gate electrode of the transistor, respectively, - forming insulating walls (11) at least on the exposed portions of the edges of said conductive layer (9), and - forming a polycrystalline silicon layer (14), characterized by the steps of - carrying out an ion implantation process using an impurity material suitable for determining a second conductivity type opposite to said first conductivity type, the atomic species of the impurity material, the concentration and the implantation energy thereof being such that the impurities can reach the substrate (1) within regions of said predetermined area in which the substrate (1) is in direct contact with said polycrystalline silicon layer (14), and can convert the polycrystalline silicon to amorphous silicon within at least a second localized region of said predetermined area, and - thermal treatment at low temperature (preferably 600°C) to cause, within a predetermined thickness measured from the substrate, an epitaxial recrystallization to monocrystalline silicon (15) of at least portions of the polycrystalline silicon layer previously converted to amorphous silicon in order to form the drain and source regions (16, 17) of the transistor.

Claim 2

A method of manufacturing an insulated gate field effect transistor (IGFET) within a predetermined area of a substrate (1) of monocrystalline silicon of a first conductivity type, comprising the steps of - forming a first insulating layer (10) in a first localized region of said predetermined area of the substrate (1), - forming a conductive layer (9) above said first insulating layer (10), - forming a second insulating layer (8) above said conductive layer (9), - wherein the first insulating layer (10) and the conductive layer (9) are intended to constitute the dielectric layer of the gate and the gate electrode of the transistor, respectively, - forming insulating walls (11) at least on the exposed portions of the edges of said conductive layer (9), and - forming a polycrystalline silicon layer (14), characterized by the steps of - carrying out an ion implantation process using an impurity material suitable for determining a second conductivity type opposite to said first conductivity type, the atomic species of the impurity material, the concentration and the implantation energy thereof being such that the impurities can reach the substrate (1) within regions of said predetermined area in which the substrate (1) is in direct contact with said polycrystalline silicon layer (14), and can convert the polycrystalline silicon to amorphous silicon within at least a second localized region of said predetermined area, and - thermal treatment at low temperature (preferably 600°C) to cause, within a predetermined thickness measured from the substrate, an epitaxial recrystallization to monocrystalline silicon (15) of at least portions of the polycrystalline silicon layer previously converted to amorphous silicon in order to form the drain and source regions (16, 17) of the transistor.

Claim 5

A method according to any of claims 1 to 3, characterized in that the thermal treatment temperature is in the range from 450°C to 600°C.