CRC calculation apparatus

Claim 1

An apparatus for generating a plurality of groups of CRC data and presenting them one group at a time in synchronism with a group clock on a CRC output bus having a number of conductors equal to the number of bits in one group comprising: means for storing a plurality of groups of CRC bits presented at a data input and having a data output for each said CRC bit; a CRC output bus having one conductor coupled to said data output for each CRC bit in the highest order CRC group; a calculation means having a data outputs coupled to said data inputs of said means for storing and having data inputs coupled to said data outputs of said means for storing and having a raw data input, said calculation means for accepting input data from said means for storing and raw input data at said raw data input and for dividing said raw iaput data by a predetermined binary number and for storing the remainder of said division in said means for storing as said CRC check bits;; and shifting means coupled to said means for storing for outputting said groups of CRC data on said CRC output bus one group at a time by shifting said CRC groups one group at a time in synchronization with said group clock signal into the highest order group position of said means for storing.

Claim 2

An apparatus for generating a plurality of groups of CRC data and presenting them one group at a time in synchronism with a group clock on a CRC output bus having a number of conductors equal to the number of bits in one group comprising: means for storing a plurality of groups of CRC bits presented at a data input and having a data output for each said CRC bit; a CRC output bus having one conductor coupled to said data output for each CRC bit in the highest order CRC group; a calculation means having a data outputs coupled to said data inputs of said means for storing and having data inputs coupled to said data outputs of said means for storing and having a raw data input, said calculation means for accepting input data from said means for storing and raw input data at said raw data input and for dividing said raw iaput data by a predetermined binary number and for storing the remainder of said division in said means for storing as said CRC check bits;; and shifting means coupled to said means for storing for outputting said groups of CRC data on said CRC output bus one group at a time by shifting said CRC groups one group at a time in synchronization with said group clock signal into the highest order group position of said means for storing.

Claim 9

An apparatus for generating a plurality of CRC groups and for outputting said CRC groups one at a time in response to a group clock signal onto a bus having a number of conductors equal to the number of bits in one group comprising: means for storing said CRC groups said storing means having a plurality of date inputs, a plurality of data outputs, and a group clock input; a CRC output bus coupled to the data outputs of the highest order group of CRC bits stored in said means for storing; a signal generation means for simultaneously performing an exclusive-OR logical operation on each bit in said highest order group of CRC bits stored in said means for storing with one bit of a group of input data and for simultaneously performing a logical AND operation between each result of the above defined exclusive-OR operations and SHIFT not signal and for generating resultant signals; and means for shifting said CRC bits in said means for storing toward the most significant CRC bit by a number of places equal to the number of bits in said group of input data and for performing an exclusive-OR logical operation between predetermined bits being shifted during predetermined shifts and the resultant signals of predetermined ones of said logical AND operations when said SHIFT not signal is in a predetermined logic state but for only shifting without any exclusive-OR operations when said SHIFT not signal is in the opposite logic state.

Claim 10

An apparatus for generating a plurality of CRC groups and for outputting said CRC groups one at a time in response to a group clock signal onto a bus having a number of conductors equal to the number of bits in one group comprising: means for storing said CRC groups said storing means having a plurality of date inputs, a plurality of data outputs, and a group clock input; a CRC output bus coupled to the data outputs of the highest order group of CRC bits stored in said means for storing; a signal generation means for simultaneously performing an exclusive-OR logical operation on each bit in said highest order group of CRC bits stored in said means for storing with one bit of a group of input data and for simultaneously performing a logical AND operation between each result of the above defined exclusive-OR operations and SHIFT not signal and for generating resultant signals; and means for shifting said CRC bits in said means for storing toward the most significant CRC bit by a number of places equal to the number of bits in said group of input data and for performing an exclusive-OR logical operation between predetermined bits being shifted during predetermined shifts and the resultant signals of predetermined ones of said logical AND operations when said SHIFT not signal is in a predetermined logic state but for only shifting without any exclusive-OR operations when said SHIFT not signal is in the opposite logic state.

Claim 14

An apparatus for generating a plurality of groups of CRC check bits in synchronization with a group clock signal and for presenting said CRC check bits at a CRC output at a rate of one group of CRC check bits per each group clock cycle through a bus having the same number of conductors as there are bits in a group comprising: a CRC checksum register having a plurality of memory cells arranged to store a plurality of groups of CRC data, each said group comprised of a plurality of CRC bits, and each memory cell having a data input, a data output and a group clock input for coupling to said group clock signal, each said memory cell for storing the data at said data input upon receipt of said group clock signal at said group clock input and for presenting said stored data at said data output; a CRC output bus coupled to said data outputs of the memory cells storing the CRC bits of the highest order group of said CRC data; a plurality of data input exclusive-OR gates, each having one input for coupling to one bit of an input data group and each having one data input coupled to said data output of one of said memory cells coupled to said CRC data output bus and each having a data output; an AND gate for each said data input exclusive-OR gate, said AND gate having a data output and each said AND gate having one input coupled to said data output of one of said data input exclusive-OR gates and each said AND gate having another input for coupling to a SHIFT not signal indicating when a straight shift without any other logical operation is to occur; a plurality of shifting links arranged into an array comprised of a number of rows equal to the number of said data input exclusive-OR gates and a number of columns equal to the number of bits in said CRC data and with each shifting link having an input and an output, said first row having its inputs coupled to the data outputs of said memory cells and said last row having its data outputs coupled to the data inputs of said memory cells, each row of shifting links comprised of a plurality of logical operators, one in each column, each logical operator for performing a shift of the bit in that logical operator's column to the next higher order bit position in the next row, selected logical operators in each row also performing an exclusive-OR operation on their incoming bits with the bit from the output of said AND gate coupled to the data output of said data input exclusive-OR gate corresponding to that row, where the data input exclusive-OR gate coupled to the most significant CRC bit corresponds to the first row and the data input exclusive-OR gate coupled to the next most significant CRC bit corresponds to the second row and so on for each row.

Claim 15

An apparatus for generating a plurality of groups of CRC check bits in synchronization with a group clock signal and for presenting said CRC check bits at a CRC output at a rate of one group of CRC check bits per each group clock cycle through a bus having the same number of conductors as there are bits in a group comprising: a CRC checksum register having a plurality of memory cells arranged to store a plurality of groups of CRC data, each said group comprised of a plurality of CRC bits, and each memory cell having a data input, a data output and a group clock input for coupling to said group clock signal, each said memory cell for storing the data at said data input upon receipt of said group clock signal at said group clock input and for presenting said stored data at said data output; a CRC output bus coupled to said data outputs of the memory cells storing the CRC bits of the highest order group of said CRC data; a plurality of data input exclusive-OR gates, each having one input for coupling to one bit of an input data group and each having one data input coupled to said data output of one of said memory cells coupled to said CRC data output bus and each having a data output; an AND gate for each said data input exclusive-OR gate, said AND gate having a data output and each said AND gate having one input coupled to said data output of one of said data input exclusive-OR gates and each said AND gate having another input for coupling to a SHIFT not signal indicating when a straight shift without any other logical operation is to occur; a plurality of shifting links arranged into an array comprised of a number of rows equal to the number of said data input exclusive-OR gates and a number of columns equal to the number of bits in said CRC data and with each shifting link having an input and an output, said first row having its inputs coupled to the data outputs of said memory cells and said last row having its data outputs coupled to the data inputs of said memory cells, each row of shifting links comprised of a plurality of logical operators, one in each column, each logical operator for performing a shift of the bit in that logical operator's column to the next higher order bit position in the next row, selected logical operators in each row also performing an exclusive-OR operation on their incoming bits with the bit from the output of said AND gate coupled to the data output of said data input exclusive-OR gate corresponding to that row, where the data input exclusive-OR gate coupled to the most significant CRC bit corresponds to the first row and the data input exclusive-OR gate coupled to the next most significant CRC bit corresponds to the second row and so on for each row.

Claim 16

A method of outputting a plurality of groups of CRC check bits one group at a time on an output bus which is only wide enough to carry one group at a time away from an apparatus for calculating CRC bits using a CRC checksum register and a calculation means comprising the steps of: calculating the CRC check bits using said calculation means and storing them in said checksum register; outputting the highest order group of CRC check bits on said output bus; shifting the second most significant group of CRC check bits into the position in said CRC checksum register formally occupied by the highest order group of CRC check bits while simultaneously shifting all lower order groups one group toward the most significant bit position; outputting the second most significant group of CRC check bits on said output bus; and continuing said shifting and outputting steps until all groups of CRC check bits have been output on said output bus.

Claim 17

A method of outputting a plurality of groups of CRC check bits one group at a time on an output bus which is only wide enough to carry one group at a time away from an apparatus for calculating CRC bits using a CRC checksum register and a calculation means comprising the steps of: calculating the CRC check bits using said calculation means and storing them in said checksum register; outputting the highest order group of CRC check bits on said output bus; shifting the second most significant group of CRC check bits into the position in said CRC checksum register formally occupied by the highest order group of CRC check bits while simultaneously shifting all lower order groups one group toward the most significant bit position; outputting the second most significant group of CRC check bits on said output bus; and continuing said shifting and outputting steps until all groups of CRC check bits have been output on said output bus.