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Patent EP0225441A2 successfully refreshed from Google Patents.
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EP0225441A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Programming current controller

Assignee: Texas Instruments Inc
•
Filing: 1986-09-17
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Granted: —
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Expires: 2006-09-17
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Abstract

Abstract An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors 38´ sets of which are coupled between associated respective source 53 and drain 54 lines, an array programming control transistor 46 and a ground select transistor 57 coupled to each of the drain 54 and source 53 lines, respectively. Each selected floating gate transistor 38´ in a programming mode is in series with control 46a, 46b, etc. and ground select transistors 57 between a high voltage Vpp and ground potential. A resistive element 42 in series with a first conducting circuit element 30 establishes a reference current which generates a voltage V₁ at the junction 44 of the resistive element 42 and the circuit element 30. In a second current leg a second conducting circuit element 32, a module floating gate transistor 38 biased into a conducting state and a module control transistor 46 are all connected between Vpp 48 and ground such that a voltage V₂ is established at the junction 35, of the second circuit element 32 and the module floating gate transistor 38. Comparing means 34 compares voltages V₁ and V₂ and adjusts the gate voltage V₃ of the module programming control transistor 46 so as to make the voltage V₂ equal to voltage V₁ and applies voltage V₃ to the gates of the array programming control transistors 46. Since the transistor 30 in the reference path is both electrically and geometrically the same as that 32 in the second leg across which the voltage developed is compared, and is made by the same process, the current in the second leg will be substantially the same as that in the reference leg. Moreover, since the array floating gate transistors 38´ are also made by the same process as is the module floating gate transistor 38 and the programming control 46 and ground select transistors 57 and also identical, by feeding the voltage V₃ to array control transistors 38´ substantially the same current will flow through a selected array transistor 38´ as flows through both the reference current path and the second current leg.

Inventors

  • 👤 Jeffrey K. Kaszubinski
  • 👤 Debra J. Dolby
  • 👤 Timmie M. Coffman
  • 👤 John F. Schreck

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 05:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 200 words
An electrically programmable semiconductor memory device of a type having an array of floating gate transistors sets of which are coupled between associated respective source and drain lines, a array programming control transistor and a ground select transistor coupled to each of said drain and source lines such that each selected floating gate transistor in a programming mode is in series with said control and ground select transistors between a high voltage Vpp, and ground potential, comprising: a resistive element in series with a first conducting circuit element connected between Vpp and ground whereby a voltage V₁ is established at the junction of said resistive element and said first conducting circuit element; a second conducting circuit element, a module floating gate transistor both biased into a conducting state and a module programming control all connected in series between Vpp and ground, whereby a voltage V₂ is established at the junction of said second circuit element and said module floating gate transistor; and means for comparing V₁ and V₂ and adjusting the gate voltage V₃ of said module control transistor so as to make the voltage V₂ equal to V₁ and applying V₃ to the gates of said array control transistors.
Claim 2
Dependent Claim 200 words
An electrically programmable semiconductor memory device of a type having an array of floating gate transistors sets of which are coupled between associated respective source and drain lines, a array programming control transistor and a ground select transistor coupled to each of said drain and source lines such that each selected floating gate transistor in a programming mode is in series with said control and ground select transistors between a high voltage Vpp, and ground potential, comprising: a resistive element in series with a first conducting circuit element connected between Vpp and ground whereby a voltage V₁ is established at the junction of said resistive element and said first conducting circuit element; a second conducting circuit element, a module floating gate transistor both biased into a conducting state and a module programming control all connected in series between Vpp and ground, whereby a voltage V₂ is established at the junction of said second circuit element and said module floating gate transistor; and means for comparing V₁ and V₂ and adjusting the gate voltage V₃ of said module control transistor so as to make the voltage V₂ equal to V₁ and applying V₃ to the gates of said array control transistors.
Claim 3
Dependent Claim 33 words
A memory device according to claim 1, wherein said first conducting circuit element and said second conducting circuit element are reference select and ground select transistors, respectively, both biased into a conducting state.
Claim 4
Dependent Claim 66 words
A memory device according to claim 2, wherein said comparing means is a comparator having one input coupled to the junction of said resistive element and said reference ground select transistor, another input coupled to the junction of said select transistor and said floating gate transistor and an output coupled to the gates of said module programming control transistor and to said array programming control transistors.
Claim 5
Dependent Claim 13 words
A memory device according to claim 3, wherein said semiconductor material is silicon.
Claim 6
Dependent Claim 22 words
A memory device according to claim 3, wherein said module programming control and array programming control transistors are P-channel field effect transistors.
Claim 7
Dependent Claim 22 words
A memory device according to claim 5, wherein said module programming control and array programming control transistors are N-channel field effect transistors.
Claim 8
Dependent Claim 33 words
A memory device according to claim 4, wherein said array programming control and floating gate transistors are made by the same process as said said module programming control and module floating gate transistors.
Claim 9
Dependent Claim 15 words
A memory device according to claim 3, wherein said resistive element is a bipolar transistor.
Claim 10
Dependent Claim 15 words
A memory device according to claim 3, wherein said resistive element is a diffusion resistor.
Claim 11
Dependent Claim 15 words
A memory device according to claim 3, wherein said resistive element is a polysilicon resistor.
Claim 12
Dependent Claim 15 words
A memory device according to claim 3, wherein said resistive element is a MOS transistor.
Claim 13
Independent Claim 182 words
A method of controlling the programming current of an array of floating gate electrically programmable read only memory transistors, comprising: establishing a desired reference current; comparing a voltage V₁ developed by said reference current across a circuit element to the voltage V₂ developed across a similar circuit element in another current path having similar circuit elements as those circuit elements in a path of a selected one of said array floating gate transistors; applying V₁ to an inverting input and V₂ to a non-inverting input of a comparator and applying the comparator output to a gate of a module programming control transistor in said circuit path such that the voltage across said control transistor varies in response to the signal output from the comparator so as to maintain the current in said another current path substantially equal to said reference current; and applying the comparator output to a gate of an array programming control transistor in series with the selected array floating gate transistor so as to maintain the current through the selected floating gate transistor substantially equal to the reference current.
Claim 14
Independent Claim 182 words
A method of controlling the programming current of an array of floating gate electrically programmable read only memory transistors, comprising: establishing a desired reference current; comparing a voltage V₁ developed by said reference current across a circuit element to the voltage V₂ developed across a similar circuit element in another current path having similar circuit elements as those circuit elements in a path of a selected one of said array floating gate transistors; applying V₁ to an inverting input and V₂ to a non-inverting input of a comparator and applying the comparator output to a gate of a module programming control transistor in said circuit path such that the voltage across said control transistor varies in response to the signal output from the comparator so as to maintain the current in said another current path substantially equal to said reference current; and applying the comparator output to a gate of an array programming control transistor in series with the selected array floating gate transistor so as to maintain the current through the selected floating gate transistor substantially equal to the reference current.
Claim 15
Dependent Claim 36 words
A method according to claim 12, wherein the circuit element in a current path of said reference current which is the same as a corresponding circuit element in said another path is a field effect transistor.
Claim 16
Dependent Claim 35 words
A method according to claim 13, wherein the circuit elements in said another current path in addition to a field effect transistor is an electrically programmable floating gate transistor and a second field effect transistor.
Claim 17
Dependent Claim 35 words
A method according to claim 14, wherein circuit elements in the current path of said reference current include a resistive element in series with the field effect transistor which is biased into a conducting state.
Claim 18
Dependent Claim 14 words
A method according to claim 13, wherein said resistive element is a bipolar transistor.
Claim 19
Dependent Claim 14 words
A method according to claim 13, wherein said resistive element is a diffusion resistor.
Claim 20
Dependent Claim 14 words
A method according to claim 13, wherein said resistive element is a polysilicon resistor.
Claim 21
Dependent Claim 14 words
A method according to claim 12, wherein said resistive element is a MOS transistor.

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