Patent EP0224717A2 successfully refreshed from Google Patents.
EP0224717A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Self-aligned channel stop
Assignee: International Business Machines Corp
•
Filing: 1986-10-28
•
Granted: —
•
Expires: 2006-10-28
Abstract
Abstract In a semiconductor structure having two highly and similarly doped, e.g., P+ type, regions (26,30) embedded in close juxtaposition in a trench-isolated N type silicon mesa (22), N+ channel stops (40,42) embedded in the N type mesa between the P type regions, are provided. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. A process of forming such channel stops introduces N type dopant into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region.
Inventors
- 👤 George Richard Goth
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:57
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A semiconductor integrated circuit structure comprising: a semiconductor substrate, preferrably monocrystalline silicon, having a first conductivity type semiconductor mesa (22) with relatively light doping which is dielectrically isolated at the surface of said substrate by a dielectric-filled trench (16); a pair of relatively highly doped second conductivity type regions (30,40;72,76) formed in a lateral or vertical spaced-apart relationship in said mesa, said regions having at least one end which butts against a common wall of said trench; characterized in that a relatively highly doped and narrow region (40; 42;78;80) of the first conductivity type is provided along said common wall between said pair of doped regions (30; 40), whereby charge leakage between said pair of doped regions via the first conductivity type semiconductor between said pair of doped regions and butting against said wall is prevented.
Claim 2
Dependent Claim
136 words
A semiconductor integrated circuit structure comprising: a semiconductor substrate, preferrably monocrystalline silicon, having a first conductivity type semiconductor mesa (22) with relatively light doping which is dielectrically isolated at the surface of said substrate by a dielectric-filled trench (16); a pair of relatively highly doped second conductivity type regions (30,40;72,76) formed in a lateral or vertical spaced-apart relationship in said mesa, said regions having at least one end which butts against a common wall of said trench; characterized in that a relatively highly doped and narrow region (40; 42;78;80) of the first conductivity type is provided along said common wall between said pair of doped regions (30; 40), whereby charge leakage between said pair of doped regions via the first conductivity type semiconductor between said pair of doped regions and butting against said wall is prevented.
Claim 3
Dependent Claim
34 words
The structure as in claim 1 wherein the dopant concentration in said narrow region is about one to two orders of magnitude higher than that in said semiconductor between said pair of doped regions.
Claim 4
Dependent Claim
29 words
The structure as in claims 1 or 2, wherein said channel stop extends to a depth which is smaller than the depths of said first and second doped regions.
Claim 5
Dependent Claim
24 words
The structure as in any of the claims 1 - 3, wherein said channel stop has a width in the range of 0.1-0.5 µm.
Claim 6
Dependent Claim
28 words
The structure as in any of the claims 1 - 4, wherein said channel stop is self-aligned to said wall and said first and second highly doped regions.
Claim 7
Dependent Claim
29 words
The structure as in any of the claims 1 - 5, wherein said trench wall is provided with an insulator liner (18,20) composed of silicon dioxide and silicon nitride.
Claim 8
Dependent Claim
11 words
The structure as in claim 6 wherein said dielectric is polyimide.
Claim 9
Dependent Claim
51 words
The structure of any of the claims 1 - 8, wherein said highly doped regions are the subcollector (72) and the emitter (76) of a transistor and said lightly doped region comprising the base and the collector, said channel stops extending vertically at said trench along said emitter and base regions.
Claim 10
Independent Claim
144 words
A method for forming a semiconductor structure in accordance with one of the claims 1 - 8, comprising the steps: providing a first conductivity type semiconductor body (86) having on the surface thereof an insulator layer (88-94); forming in said insulator layer an opening (98) to expose said body corresponding to where a trench is desired; forming a blockout mask (104) having an opening therein to limit the exposure of said body exposed by said opening in said insulator layer to a selected portion thereof; introducing dopant (108) of the first conductivity type into said body exposed by the resultant of the openings in said insulator and blockout mask; annealing to laterally diffuse said dopant into said body; and reactively ion etching said exposed body to form said trench whereby is formed a highly doped first conductivity type channel stop (114;116) in said body.
Claim 11
Dependent Claim
15 words
The method as in claim 9 wherein said dopant introduction is accomplished by ion implantation.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.