Patent EP0224626A1 successfully refreshed from Google Patents.
EP0224626A1
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EP
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Multi-signal processor synchronized system
Assignee: Compagnie IBM France SAS
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Filing: 1985-10-30
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Granted: —
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Expires: 2005-10-30
Abstract
Abstract The system is made to concentrate n voice signals over a same high speed channel using a single Unit Processor. The data transfers between the Unit Processor and a set of Signal Processors are managed by a counter loaded by the Unit Processor with a predetermined value selected according to the system architecture. The counter is made of two parts serially connected , the first one made for sequentially providing an interrupt request to the Unit Processor and the second one driving a decoder providing signals for serially scanning the set of signal processors and providing time slots for data transfers between Unit Processor and Signal Processors.
Inventors
- 👤 Alain Blanc
- 👤 Patrick Jeanniot
- 👤 Sylvie Spalmacin-Roma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 12:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G06F13/00; G06F13/14; G06F13/20; G06F13/22; H; H04; H04B; H04B1/00; H04B1/66; H04B1/667; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04M; H04M1/00; H04M1/253
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
113 words
A system for synchronizing the operation of a set of signal processors connected to a common unit processor operating as a system managing device said system including: - an I/O Bus connected to said Unit Processor (20); - a Signal Processor Adapter (SPA) (22) connected to said I/O bus; - a Data Exchange (D.E.) Bus connected to said SPA; said set of signal processors being connected to said Signal Processor Adapter through said D.E. Bus; said SPA including means for generating Unit Processor interrupt request on a cyclic basis, and means for sequentially scanning the set of signal processors to control data exchanges between said Unit Processor and each of said signal processors.
Claim 2
Independent Claim
113 words
A system for synchronizing the operation of a set of signal processors connected to a common unit processor operating as a system managing device said system including: - an I/O Bus connected to said Unit Processor (20); - a Signal Processor Adapter (SPA) (22) connected to said I/O bus; - a Data Exchange (D.E.) Bus connected to said SPA; said set of signal processors being connected to said Signal Processor Adapter through said D.E. Bus; said SPA including means for generating Unit Processor interrupt request on a cyclic basis, and means for sequentially scanning the set of signal processors to control data exchanges between said Unit Processor and each of said signal processors.
Claim 3
Dependent Claim
78 words
A system according to claim 1 wherein said Signal Processor Adapter is further characterized in that it includes: - a System Synchronization Register SSR means operating as a counter; - means for program loading said counter to define a count cycle; - decoding means connected to said SSR, and, means for generating logic signals for sequentially scanning the set of signal processors, whereby data transfer operations to and from signal processors and the Unit Processor are being synchronized.
Claim 4
Dependent Claim
50 words
A system according to claim 2 further characterized in that said System Synchronization Register means operating as a counter is made to be split into two parts, serially connected to each other, with first part generating a carry bit to be used as and interrupt request to the Unit Processor.
Claim 5
Dependent Claim
41 words
A system according to claim 1, 2 or 3 further characterized in that said signal processor is made to include dual buffering means for data transfers from and to said Data Exchange Bus, with said buffers operating on a ping-pong basis.
Claim 6
Dependent Claim
51 words
A system according to claim 4 further characterized in that said signal processor is connected to voice terminals both for input and output purposes, through A/D and D/A coders, with the connections to said D/A and from said A/D being each made through dual buffers alternatively operating on a ping-pong basis.
Claim 7
Dependent Claim
22 words
A system according to claim 5 further characterized in that said SSR counter provides a bit used to control said ping-pong operations.
Claim 8
Dependent Claim
38 words
A system according to claim 5 wherein said signal processors are individually made to process with A/D PCM coded Voice signals using block companded (BCPCM) techniques over predetermined length voice segments or predetermined blocks of PCM coded samples.
Claim 9
Independent Claim
48 words
A system according to any one of claims 5 through 7 wherein the Voice signals individually processed by the signal processors attached to a same Unit Processor are made to be concentrated over a high speed channel through a high speed communication adapter connected to the I/O Bus.
References Cited (Backward Citations)
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