Sense amplifier for a non-volatile memory

Claim 2

A memory having an array of non-volatile memory cells which are in either a programmed or unprogrammed state, wherein the programmed state is characterized as having a first conductivity and the unprogrammed state is characterized as having a second conductivity, comprising: decoder means for selecting a memory cell in response to an address and for coupling said selected memory cell to a common data line; a reference memory cell which is unprogrammed and has the second conductivity; a first transistor having a first current electrode coupled to a first power supply terminal, and a second current electrode and a control electrode coupled to the data line, whereby a logic state current flows through said first transistor of a magnitude related to the conductivity of the selected memory cell; a second transistor having a first current electrode coupled to the first power supply terminal, and a second current electrode and a control electrode coupled to the reference memory cell, whereby a reference current flows through said second transistor of a magnitude related to the second conductivity; and comparison means for comparing the logic state current to the reference current and for providing an output signal at a first logic state when the logic state current is proportional to the first conductivity and for providing the output signal at a second logic state when the logic state current is proportional to the second conductivity.

Claim 3

The memory of claim l further comprising disable means for disabling the comparator for a predetermined time duration following the decoder means receiving the address.

Claim 4

A memory having an array of non-volatile memory cells which are in either a programmed or unprogrammed state, wherein the programmed state is characterized as having a first conductivity and the unprogrammed state is characterized as having a second conductivity, comprising: decoder means for selecting a memory cell in response to an address and for coupling said selected memory cell to a common data line; a reference memory cell which is unprogrammed and has the second conductivity; current reference means, coupled to the reference memory cell, for establishing a reference current proportional to the second conductivity; logic state current means, coupled to the data line, for establishing a logic state current related to the conductivity of the selected memory cell; a first current mirror slave, coupled to the reference current means, for establishing a reference current limit between a first power supply node and an output node as a predetermined proportion of the reference current; a second current mirror slave, coupled to the logic state current means, for establishing a control current limit between a second power supply terminal and the output node as a predetermined proportion of the logic state current, said control current limit being of a first magnitude if the logic state current is related to the first conductivity and being of a second magnitude if the logic state current is related to the second conductivity; and output means, coupled to the output node, for providing an output signal at a first logic state when the second current mirror slave establishes the control current limit at the first magnitude, and for providing the output signal at a second logic state when the second current mirror slave establishes the control current limit at the second magnitude.

Claim 5

A memory having an array of non-volatile memory cells which are in either a programmed or unprogrammed state, wherein the programmed state is characterized as having a first conductivity and the unprogrammed state is characterized as having a second conductivity, comprising: decoder means for selecting a memory cell in response to an address and for coupling said selected memory cell to a common data line; a reference memory cell which is unprogrammed and has the second conductivity; current reference means, coupled to the reference memory cell, for establishing a reference current proportional to the second conductivity; logic state current means, coupled to the data line, for establishing a logic state current related to the conductivity of the selected memory cell; a first current mirror slave, coupled to the reference current means, for establishing a reference current limit between a first power supply node and an output node as a predetermined proportion of the reference current; a second current mirror slave, coupled to the logic state current means, for establishing a control current limit between a second power supply terminal and the output node as a predetermined proportion of the logic state current, said control current limit being of a first magnitude if the logic state current is related to the first conductivity and being of a second magnitude if the logic state current is related to the second conductivity; and output means, coupled to the output node, for providing an output signal at a first logic state when the second current mirror slave establishes the control current limit at the first magnitude, and for providing the output signal at a second logic state when the second current mirror slave establishes the control current limit at the second magnitude.

Claim 6

The memory of claim 3, wherein the current mirror reference means comprises: a first transistor having a first current electrode coupled to the second power supply terminal, and a control electrode and a second current electrode coupled to the reference memory cell; a second transistor having a first current electrode coupled to the second power supply terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode; and a third transistor having a first current electrode coupled to the first power supply terminal, and a control electrode and a second current electrode coupled to the second current electrode of the second transistor and to the first current mirror slave.

Claim 7

The memory of claim 4 wherein the logic state current means comprises a fourth transistor having a first current electrode coupled to the second power supply terminal, and a control electrode and a second current electrode coupled to the second current mirror slave and to the common data line.

Claim 8

The memory of claim 5 wherein the first current mirror slave comprises a fifth transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the output node.

Claim 9

The memory of claim 6 wherein the second current mirror slave comprises a sixth transistor having a first current electrode coupled to the second power supply terminal, a control electrode coupled to the control electrode of the fourth transistor, and a second current electrode coupled to the output node.

Claim 10

The memory of claim 7 further comprising: reference voltage generator means for generating a reference voltage; and a seventh transistor, interposed between the fourth transistor and the common data line, having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode for receiving the reference voltage, and a second current electrode coupled to the common data line.

Claim 11

In a memory having an array of non-volatile memory cells which are in either a programmed or unprogrammed state, wherein the programmed state is characterized as having a first conductivity and the unprogrammed state is characterized as having a second conductivity, a method for detecting the state of a selected memory cell, comprising the steps of: selecting a memory cell in response to an address; providing a reference memory cell which is unprogrammed and has the second conductivity; establishing a reference current proportional to the second conductivity through the reference memory cell; establishing a logic state current related to the conductivity of the selected memory cell through the selected memory cell; establishing a reference current limit between a first power supply terminal and an output node as a predetermined proportion of the reference current; establishing a control current limit between a second power supply terminal and the output node as a predetermined proportion of the logic state current, said control current limit being a first magnitude if the selected memory cell has the first conductivity and a second magnitude if the selected memory cell has the second conductivity; and providing an output signal at a first logic state if the the current between the second power supply terminal and the output node is limited to the second magnitude and providing the output signal at a second logic state if the current between the second power supply terminal and the output node is limited to the third magnitude.

Claim 12

In a memory having an array of non-volatile memory cells which are in either a programmed or unprogrammed state, wherein the programmed state is characterized as having a first conductivity and the unprogrammed state is characterized as having a second conductivity, a method for detecting the state of a selected memory cell, comprising the steps of: selecting a memory cell in response to an address; providing a reference memory cell which is unprogrammed and has the second conductivity; establishing a reference current proportional to the second conductivity through the reference memory cell; establishing a logic state current related to the conductivity of the selected memory cell through the selected memory cell; establishing a reference current limit between a first power supply terminal and an output node as a predetermined proportion of the reference current; establishing a control current limit between a second power supply terminal and the output node as a predetermined proportion of the logic state current, said control current limit being a first magnitude if the selected memory cell has the first conductivity and a second magnitude if the selected memory cell has the second conductivity; and providing an output signal at a first logic state if the the current between the second power supply terminal and the output node is limited to the second magnitude and providing the output signal at a second logic state if the current between the second power supply terminal and the output node is limited to the third magnitude.

Claim 13

l0. The method of claim 9 further comprising the step of holding the output node to a predetermined voltage level for a predetermined time duration after an address transition.