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EP0223714A2
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Semiconductor integrated circuit device with test circuit
Assignee: Fujitsu Ltd
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Filing: 1986-11-20
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Granted: —
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Expires: 2006-11-20
Abstract
Abstract A semiconductor integrated circuit device with a test circuit including : a plurality of basic gate cells (Gi) arranged in a matrix ; wiring connected between the basic gate cells and arranged so as to constitute a logic circuit ; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells. The test circuit comprises : a test input section having a plurality of row selection wires (Sci, Scn) provided along the basic gate cells in a row direction, a plurality of column selection wires (Sli, Sln) provided along the basic gate cells in a column direction, and an access circuit (Ali) connected to an input portion of the basic gate cell for applying an input signal to the basic gate cell optionally selected by the row and column selection wires ; and a test detection section having a plurality of monitor wires ; and a test detection section having a plurality of monitor wires (Mi, Mn) provided along the basic gate cells in the row direction and a switching element (DI) connected between the basic gate cell (Gi) and the monitor wire (Mi).
Inventors
- 👤 Tetsu Tanizawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
164 words
A semiconductor integrated circuit device with a test circuit comprising: a plurality of basic gate cells arranged in a matrix; wiring means connected between said basic gate cells so as to constitute a logic circuit; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells, said test circuit comprising: a test input means having a plurality of row selection wires provided along said basic gate cells in a row direction, a plurality of column selection wires provided along said basic gate cells in a column direction, and access means connected to an input portion of said basic gate cell for applying an input signal to said basic gate cell optionally selected by said row and column selection wires; and a test detection means having a plurality of monitor wires provided along said basic gate cells in the row direction and a switching means connected between said basic gate cell and said monitor wire.
Claim 2
Dependent Claim
164 words
A semiconductor integrated circuit device with a test circuit comprising: a plurality of basic gate cells arranged in a matrix; wiring means connected between said basic gate cells so as to constitute a logic circuit; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells, said test circuit comprising: a test input means having a plurality of row selection wires provided along said basic gate cells in a row direction, a plurality of column selection wires provided along said basic gate cells in a column direction, and access means connected to an input portion of said basic gate cell for applying an input signal to said basic gate cell optionally selected by said row and column selection wires; and a test detection means having a plurality of monitor wires provided along said basic gate cells in the row direction and a switching means connected between said basic gate cell and said monitor wire.
Claim 3
Dependent Claim
72 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said test circuit further comprises: row selection means, operatively connected to said row selection wires, for selecting any of said row selection wires; column selection means, operatively connected to said column selection wires, for selecting any of said column selection wires; and monitor means, operatively connected to said monitor wires, for detecting levels of said monitor wires.
Claim 4
Dependent Claim
115 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said test input means further comprises: a plurality of additional row selection wires provided along said basic gate cells in the row direction, each of said basic gate cells being operatively connected to said additional row selection wire; a plurality of additional column selec tion wires provided along said basic gate cells in the column direction, each of said basic gate cells being operatively connected to said additional column selection wire; and additional access means having input terminals connected to said additional row selection wire and said additional column selection wire, and an output terminal connected to said gate cell.
Claim 5
Dependent Claim
28 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said basic gate cell comprises a NAND gate or a NOR gate circuit.
Claim 6
Dependent Claim
37 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l or 4, wherein said access means is constituted by at least one emitter of an input multi-emitter transistor in said NAND gate circuit.
Claim 7
Dependent Claim
42 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, 4 or 5, wherein said access means is constituted by at least one diode connected to a base of said input multi-emitter transistor in said NAND gate circuit.
Claim 8
Dependent Claim
37 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l or 4, wherein said access means is constituted by at least one base of an input PNP-type transistor in said NAND gate circuit.
Claim 9
Dependent Claim
21 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said switching means comprises a diode.
Claim 10
Dependent Claim
21 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said switching means comprises a transistor.
Claim 11
Dependent Claim
37 words
l0. A semiconductor integrated circuit device with a test circuit as claimed in claim 3 or 4, wherein said additional access means is constituted by a base of a multi-collector transistor connected to said NAND gate circuit.
Claim 12
Dependent Claim
28 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l, wherein said access means can set said basic gate cell to an enabling state.
Claim 13
Dependent Claim
66 words
A semiconductor integrated circuit device with a test circuit as claimed in claim 3, wherein said additional access means can forcibly set the output of said basic gate cell to either a low or a high level, i.e., when the NAND gate is used, the level is low, and when the NOR gate is used, the level is high, and can disconnect from said monitor wire.
Claim 14
Dependent Claim
165 words
A semiconductor integrated circuit device with a test circuit comprising: a plurality of basic gate cells arranged in a matrix; wiring means connected between said basic gate cells so as to constitute a logic circuit, said wiring means being arranged so as to inhibit interconnection between basic gate cells provided along a column direction; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells, said test circuit comprising: a test input means having a plurality of column selection wires provided along said basic gate cells in a column direction, and access means connected to an input portion of said basic gate cell for applying an input signal to said basic gate cell optionally selected by said column selection wires; and a test detection means having a plurality of monitor wires provided along said basic gate cells in the row direction and a switching means connected between said basic gate cell and said monitor wire.
Claim 15
Dependent Claim
165 words
A semiconductor integrated circuit device with a test circuit comprising: a plurality of basic gate cells arranged in a matrix; wiring means connected between said basic gate cells so as to constitute a logic circuit, said wiring means being arranged so as to inhibit interconnection between basic gate cells provided along a column direction; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells, said test circuit comprising: a test input means having a plurality of column selection wires provided along said basic gate cells in a column direction, and access means connected to an input portion of said basic gate cell for applying an input signal to said basic gate cell optionally selected by said column selection wires; and a test detection means having a plurality of monitor wires provided along said basic gate cells in the row direction and a switching means connected between said basic gate cell and said monitor wire.
Claim 16
Dependent Claim
55 words
A semiconductor integrated circuit device with a test circuit as claimed in claim l3, wherein said test circuit further comprises: column selection means, operatively connected to said column selection wires, for selecting any of said column selection wires, and monitor means, operatively connected to said monitor wires, for detecting a level of said monitor wire.
References Cited (Backward Citations)
No citation records indexed.
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