Patent US1141089A successfully refreshed from Google Patents.
Patent EP0222326A2 successfully refreshed from Google Patents.
EP0222326A2
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EP
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Method of fabricating an improved insulated gate semiconductor device
Assignee: General Electric Co
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Filing: 1986-11-06
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Granted: —
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Expires: 2006-11-06
Abstract
Abstract To provide a MOSFET power switching device with a low on-resistance, the body regions of active MOSFET cells are formed through a pre-existing continuous high conductivity zone created immediately adjacent the surface of a common drain region. This zone retards the depth of diffusion of the cell body regions to achieve a shorter MOSFET channel length and also forms lower resistivity portions of the device main or forward current paths; both factors contributing a lowering of the device on-resistance.
Inventors
- 👤 Hamza Yilmaz
- 👤 Claudia Gail Borman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D30/662; H10D62/17; H10D62/393
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
163 words
A process for fabricating a power semiconductor device, comprising: providing a chip of silicon semiconductor material including a first region of a first conductivity type having a substantially uniform impurity concentration level and an upper surface; forming a continuous, high conductivity zone of said first conductivity type immediately adjacent said upper surface of said first region, said zone having an impurity concentration level higher than that of said first region; depositing impurities of a second conductivity type through said high conductivity zone and into said first region to form discrete body regions for active cells of said power semiconductor device; and depositing impurities of said first conductivity type into said body regions to form at least one source region in each said active cell spaced from said zone by an intervening portion of said body region such that forward device current conducted through a channel formed in said intervening body region portion flows into said first region through said high . conductivity zone.
Claim 2
Dependent Claim
163 words
A process for fabricating a power semiconductor device, comprising: providing a chip of silicon semiconductor material including a first region of a first conductivity type having a substantially uniform impurity concentration level and an upper surface; forming a continuous, high conductivity zone of said first conductivity type immediately adjacent said upper surface of said first region, said zone having an impurity concentration level higher than that of said first region; depositing impurities of a second conductivity type through said high conductivity zone and into said first region to form discrete body regions for active cells of said power semiconductor device; and depositing impurities of said first conductivity type into said body regions to form at least one source region in each said active cell spaced from said zone by an intervening portion of said body region such that forward device current conducted through a channel formed in said intervening body region portion flows into said first region through said high . conductivity zone.
Claim 3
Dependent Claim
28 words
The process defined in Claim 1, wherein said high conductivity zone is formed in said first region by ion implantation to a depth of 0.25 to 6 microns.
Claim 4
Dependent Claim
29 words
The process defined in Claim 1, wherein said high conductivity zone is formed to a depth comparable to the ultimate depth of said intervening portion of said body regions.
Claim 5
Dependent Claim
29 words
The process defined in Claim 1, wherein the impurity concentration of said high conductivity zone is at least five times greater than the impurity concentration of said first region.
Claim 6
Dependent Claim
45 words
The process defined in Claim 4, wherein said high conductivity zone is formed in said first region by an ion implantation dose of from 5 x 10 10 to 1 x 10 14 particles per centimeter squared of an impurity of said first conductivity type.
Claim 7
Dependent Claim
56 words
The process defined in Claim 5, wherein said discrete body regions are formed by an ion implantation dose of about 1 x 10 13 to 5 x 10 14 particles per centimeter squared of an impurity of said second conductivity type followed by a diffusion drive of 1000 - 1100 . C for-six to ten hours.
Claim 8
Dependent Claim
30 words
The process defined in Claim 6, wherein said high conductivity zone is implantated to a depth approximately equal to the ultimate depth of said intervening portion of said body regions.
Claim 9
Dependent Claim
29 words
The process defined in Claim 7, wherein said body regions are formed having a deep well portion of a depth greater and higher impurity concentration than said intervening portion.
Claim 10
Dependent Claim
23 words
The process defined in Claim 8, wherein a pair of source regions are formed in each said body region using DMOS fabrication techniques.
Claim 11
Dependent Claim
35 words
The process defined in Claim 9, which further includes the step of forming a high voltage blocking region in said first region at a location laterally adjacent said active cells of said power semiconductor device.
References Cited (Backward Citations)
No citation records indexed.
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