Random access memory system

Claim 2

Random access memory system, comprising at least a pair of memory array chips (28), access means, decoder and a register (38), characterized by means responsive to a first address (48, 50) for applying a first group of bits from one of said chips to a first portion of said register (38), means (66, 68) responsive to a second address (48, 52) for applying a second group of bits from another of said chips to a second portion of said register (38), means (58, 60) for determining a starting address for a block transfer of bits from said register (38), and means (64, 70) responsive to said determining means for providing said first and second address (50, 52) according to the value of said starting address.

Claim 3

Memory system as recited in Claim 1, characterized by means (Fig. 13) for sequentially transferring in said block transfer said bits applied to said register by said means responsive to said first and second addresses.

Claim 4

Memory system as set forth in claims 1 to 2, characterized by a first plurality of memories (28), each providing a second plurality of outputs according to one address, said memories containing a third plurality of memory blocks of data, each said block being distributed over a fourth plurality of said addresses in all of said first plurality of memories, any bit of data in any of said memories being uniquely identified by a target address, intermediate storing means, means for sequentially transferring a memory block con­taining a bit identified by one said target address from said memories to said intermediate storage means in parallel transfers of a product of said first and second pluralities, the first said parallel transfer containing said one identified bit, each said transfer consisting of bits having contiguous addresses, a bit at one end of a block being contiguous with a bit at another end of said block, and means for outputting said memory block from said inter­mediate storing means in a sequence of contiguous bits beginning with said identified bit.

Claim 5

Memory system, as set forth in claims 1 to 3, characterized by a first plurality of memories (28), each providing a second plurality of output bits according to one chip address, said chip address being divided into a high order chip address and a low order chip address, a first register (38) receiving in parallel said second plurality of output bits from said plurality of memories, said first register comprising a third plurality of first latches, said third plurality being a product of said first plurality and said second plurality, a second register (40) receiving in parallel outputs of said first register, said second register comprising said third plurality of second latches, first means (44, 58) for transferring a bit from any of said first and second latches to a single bit output line, and means (42, 60) for simultaneously addressing said plura­lity of memories responsive to a starting address, wherein said high order chip addresses are common to all of said memories and said low order chip addresses may vary among said memories.

Claim 6

Memory system as set forth in Claim 4, wherein said first transferring means (58) transfers a block of a fourth plurality of bits in a sequence beginning at any starting point in said block according to said starting address, and said fourth plurality is greater than said third plurality, and further comprising second means (60) for transferring a fifth plurality of third pluralities of bits from said memories to said first register, wherein each of said fifth pluralities of bits consists of bits in the other of said sequence and the first of said fifth plu­ralities of bits includes a bit identified with said starting point.

Claim 7

Memory system as recited in Claims 1 to 4, wherein said first transferring means (58) is responsive to a low order portion of said starting address for deter­mining said starting point of said sequence, and wherein said second transferring means (60) is responsive to a high order portion of said starting address, said high order chip address consisting of a part of said high order portion exclusive of said low order portion (66, 68), and further comprising means (62, 64, 70) for deriving said low order chip addresses from a first part of said higher order portion and a second part of said lower order portion, said first and second parts being of neighbouring orders.