Patent EP0220410A2 successfully refreshed from Google Patents.
EP0220410A2
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EP
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A dynamic random access memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
Assignee: International Business Machines Corp
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Filing: 1986-08-22
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Granted: —
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Expires: 2006-08-22
Abstract
Abstract Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.
Inventors
- 👤 Nicky Chau-Chun Lu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 18:58
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10B12/373; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10W; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
113 words
A dynamic random access memory device having a single-crystal transistor structure on a trench storage capacitor structure comprising: a single-crystal silicon substrate, a trench storage capacitor disposed in said substrate including a region of doped polysilicon material bounded by a wall of insulation material, a single-crystal epitaxial silicon layer disposed on said substrate, an access transistor device disposed over said trench capacitor, said access transistor device having a source/drain region formed from said single-crystal epitaxial silicon layer material, and a polysilicon region disposed in a window in said single-crystal epitaxial silicon layer over said trench capacitor for connecting said source of said access transistor to said doped polysilicon material of said trench capacitor.
Claim 2
Dependent Claim
113 words
A dynamic random access memory device having a single-crystal transistor structure on a trench storage capacitor structure comprising: a single-crystal silicon substrate, a trench storage capacitor disposed in said substrate including a region of doped polysilicon material bounded by a wall of insulation material, a single-crystal epitaxial silicon layer disposed on said substrate, an access transistor device disposed over said trench capacitor, said access transistor device having a source/drain region formed from said single-crystal epitaxial silicon layer material, and a polysilicon region disposed in a window in said single-crystal epitaxial silicon layer over said trench capacitor for connecting said source of said access transistor to said doped polysilicon material of said trench capacitor.
Claim 3
Dependent Claim
32 words
A dynamic memory device according to claim 1 wherein said substrate includes a heavily doped P+ doped silicon wafer and a P- epitaxial silicon layer disposed on said P+ doped silicon wafer.
Claim 4
Independent Claim
184 words
A method for fabricating a dynamic random access memory device having a single-crystal transistor device on a trench storage capacitor structure, comprising the steps of: Step 1. forming a mask layer on a single-crystal silicon substrate; Step 2. opening a window in said mask layer and etching a trench in said substrate beneath said window; Step 3. filling said trench with polysilicon material and doping said polysilicon material; Step 4. forming a layer of oxide over said polysilicon filled trench; Step 5. removing said mask layer from said substrate; Step 6. growing a doped epitaxial single-crystal silicon layer over said substrate and oxide covered trench regions; Step 7. forming a mask layer over said epitaxial silicon layer; Step 8. opening a window in said mask layer over said trench region and etching away said epitaxial silicon and oxide over said trench; Step 9. refilling said window formed in step 8 with polysilicon material; Step 10. removing said mask layer formed in step 7; Step 11. forming a access transistor device over said trench by conventional gate oxide growth and definition, and source/drain dopant implantation.
Claim 5
Independent Claim
184 words
A method for fabricating a dynamic random access memory device having a single-crystal transistor device on a trench storage capacitor structure, comprising the steps of: Step 1. forming a mask layer on a single-crystal silicon substrate; Step 2. opening a window in said mask layer and etching a trench in said substrate beneath said window; Step 3. filling said trench with polysilicon material and doping said polysilicon material; Step 4. forming a layer of oxide over said polysilicon filled trench; Step 5. removing said mask layer from said substrate; Step 6. growing a doped epitaxial single-crystal silicon layer over said substrate and oxide covered trench regions; Step 7. forming a mask layer over said epitaxial silicon layer; Step 8. opening a window in said mask layer over said trench region and etching away said epitaxial silicon and oxide over said trench; Step 9. refilling said window formed in step 8 with polysilicon material; Step 10. removing said mask layer formed in step 7; Step 11. forming a access transistor device over said trench by conventional gate oxide growth and definition, and source/drain dopant implantation.
Claim 6
Dependent Claim
46 words
A method according to claim 3 wherein said epitaxial layer grown in Step 6 is grown from single-crystal seeds from said single-crystal silicon substrate to provide a single-crystal epitaxial layer, and wherein said access transistor device formed in Step 11 is composed of said single-crystal material.
Claim 7
Dependent Claim
17 words
A method according to claim 4 wherein said single-crystal silicon substrate is a heavily P+ doped wafer.
Claim 8
Dependent Claim
26 words
A method according to claim 4 wherein said single-crystal silicon substrate further includes a P- epitaxial layer disposed on top of said heavily P+ doped wafer.
Claim 9
Dependent Claim
24 words
A method according to claim 4 wherein said mask layer formed in Step 1 is a composite layer of silicon oxide and silicon nitride.
Claim 10
Dependent Claim
54 words
A method according to claim 4 wherein a composite layer of silicon oxide and silicon nitride on silicon oxide is formed on the surfaces of the trench etched in Step 2 prior to filling said trench with polysilicon material in Step 3, said composite layer providing an insulation layer for said trench storage capacitor.
Claim 11
Dependent Claim
39 words
A method according to claim 4 wherein said Step 11 further includes heavily doping said polysilicon material refilled in Step 9 for providing a connection from the source of said access transistor to said polysilicon material in said trench.
References Cited (Backward Citations)
No citation records indexed.
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