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EP0219907A1
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Integrated memory circuit
Assignee: Koninklijke Philips NV
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Filing: 1986-10-13
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Granted: —
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Expires: 2006-10-13
Abstract
Abstract An integrated memory circuit includes a memory loop which comprises two gates which are controlled by a clock signal. The circuit is susceptible to a race condition, so that correct operation cannot always be ensured. The "race" problem is solved by choosing the switching thresholds of the gate inputs receiving the clock signal so that the gates respond successively instead of (sustantially) simultaneously to the clock signal. The correct switching sequence of the gates and the correct operation of the memory circuit can thus be ensured.
Inventors
- 👤 Bernardus Henricus Jozef Cornelissen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:03
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
76 words
An integrated memory circuit, including a clock input for receiving a clock signal, a data input for receiving a data bit under the control of the clock signal, and a data output, the memory circuit also including a memory loop comprising a first and a second gate, characterized in that both gates can be switched by the clock signal, the switching threshold of the first gate deviating substantially from the switching threshold of the second gate.
Claim 2
Dependent Claim
76 words
An integrated memory circuit, including a clock input for receiving a clock signal, a data input for receiving a data bit under the control of the clock signal, and a data output, the memory circuit also including a memory loop comprising a first and a second gate, characterized in that both gates can be switched by the clock signal, the switching threshold of the first gate deviating substantially from the switching threshold of the second gate.
Claim 3
Dependent Claim
79 words
An integrated memory circuit as claimed in Claim 1, characterized in that the first gate includes a first input which is connected to the output of the second gate and a second input which is connected to the clock input, the output of the first gate being connected to a first input of the second gate which includes a second input which is connected to the clock input and a third input which is connected to the data input.
Claim 4
Dependent Claim
93 words
An integrated memory circuit as claimed in Claim 1 or 2, characterized in that the memory circuit includes complementary MOS transistors, both gates including an input for the clock signal whereto the gate electrodes of an assembly formed by a P-channel MOS transistor and an N-channel MOS transistor are connected, the ratio of the conductivity factors of said P-channel and N-channel MOS transistors of the assembly of the first gate deviating substantially from the ratio of the conductivity factors of the P-channel and N-channel MOS transistors of the assembly of the second gate.
Claim 5
Dependent Claim
87 words
An integrated memory circuit as claimed in Claim 3, characterized in that the first gate includes a NAND-gate, the second gate including a gate combination whose output generates the logic inverse of the result of the logic AND-function performed on the signal on its first input and the result of the logic OR-function performed on the signals on its second and third inputs, the switching threshold of said assembly of the first gate being substantially lower than the switching threshold of said assembly of the second gate.
Claim 6
Dependent Claim
47 words
An integrated memory circuit as claimed in Claim 4, characterized in that for a supply voltage of 5 volts the switching threshold of said assembly of the first gate is between 0.5 and 1.5 volts lower than the switching threshold of said assembly of the second gate.
Claim 7
Dependent Claim
87 words
An integrated memory circuit as claimed in Claim 3, characterized in that the first gate includes a NOR-gate, the second gate including a gate combination whose output generates the logic inverse of the result of the logic OR-function performed on the signal on its first input and the result of the logic AND-function performed on the signals on its second and third inputs, the switching threshold of said assembly of the first gate being substantially higher than the switching threshold of said assembly of the second gate.
Claim 8
Dependent Claim
47 words
An integrated memory circuit as claimed in Claim 6, characterized in that for a supply voltage of 5 volts the switching threshold of said assembly of the first gate is between 0.5 and 1.5 volts higher than the switching threshold of said assembly of the second gate.
Claim 9
Dependent Claim
17 words
An integrated flipflop circuit including a memory circuit as claimed in any one of the preceding Claims.
Claim 10
Dependent Claim
45 words
An integrated flipflop circuit as claimed in Claim 8, characterized in that the flipflop circuit includes a cascade connection of a memory circuit as claimed in Claim 4 and a memory circuit as claimed in Claim 6, both memory circuits receiving the same clock signal.
Claim 11
Dependent Claim
13 words
A shift register including an integrated flipflop circuit as claimed in Claim 9.
References Cited (Backward Citations)
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