Patent EP0218830A2 successfully refreshed from Google Patents.
EP0218830A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A memory test apparatus
Assignee: Hitachi Ltd
•
Filing: 1986-08-06
•
Granted: —
•
Expires: 2006-08-06
Abstract
Abstract To provide a memory test apparatus enabling to test a high-performance memory having two or more memory functions, the apparatus of the present invention includes a pattern generator (l5) for generating an algorithmic pattern to be inputted to a first memory block (2) having a first memory function of a memory under test (l) having at least two memory functions, an auxiliary pattern generator (l6) for storing an output (7) from the algorithmic pattern generator (l5) and for outputting an expected value (25) to a second memory block (3) having a second memory function of the memory (l) at a preset timing based on the stored output (7), a comparator (l7) for comparing outputs (l0, ll) from the first and second memory blocks (2, 3) with expected values for the memory functions, respectively, and a memory (20) for storing an output (27, 28) from the comparator (l7). Since algorithmic pattern generator (l5) and the auxiliary pattern generator (l6) are included, the present invention has such an effect that even if the first and second memory blocks (2, 3) of the memory under test (l) operate asynchronously, the data transfer function therebetween and the performance related to the operation timing can be tested and that a highly precise memory test apparatus can be provided.
Inventors
- 👤 Ikuo Kawaguchi
- 👤 Yoshihiko Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:37
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
107 words
A memory test apparatus comprising: means (l5) for generating an algorithmic pattern to be inputted to a first block (2) of a memory under test (l); auxiliary pattern generate means (l6) for storing an output from said algorithmic pattern generate means (l5) and for outputting an expected value for a second block (3) of the memory (l) at a preset timing based on the stored output; means (l7) for comparing outputs from said first and second blocks (2, 3) of the memory (l) with expected values for said first and second blocks (2, 3), respectively; and memory means for storing an output from said compare means (l7).
Claim 2
Dependent Claim
107 words
A memory test apparatus comprising: means (l5) for generating an algorithmic pattern to be inputted to a first block (2) of a memory under test (l); auxiliary pattern generate means (l6) for storing an output from said algorithmic pattern generate means (l5) and for outputting an expected value for a second block (3) of the memory (l) at a preset timing based on the stored output; means (l7) for comparing outputs from said first and second blocks (2, 3) of the memory (l) with expected values for said first and second blocks (2, 3), respectively; and memory means for storing an output from said compare means (l7).
Claim 3
Dependent Claim
56 words
A memory test apparatus according to Claim l, wherein said auxiliary pattern generate means (l6) contains a content equal to a content of said first block (2) of the memory under test (l) and outputs as an expected value a pattern identical to a pattern transferred from said first block (2) to said second block (3).
Claim 4
Dependent Claim
21 words
A memory test apparatus according to Claim l, wherein said second block (3) of the memory (l) is a shift register.
Claim 5
Dependent Claim
45 words
A memory test apparatus according to Claim l, wherein said auxiliary pattern generate means (l6) receives an address signal and an input data outputted from said algorithmic pattern generate means (l5) and includes a plurality of pattern memory units (33-35) for storing the input data.
Claim 6
Dependent Claim
23 words
A memory test apparatus according to Claim 4, wherein said address signal comprises an X address signal and a Y address signal (6).
Claim 7
Dependent Claim
83 words
A memory test apparatus according to Claim l, wherein said auxiliary pattern generate means (l6) receives an address signal and an input data outputted from said algorithmic pattern generate means (l5), outputs a fail memory address signal (26) to a memory (20) in which the output from said compare means (l7) is stored, and outputs a generation completion signal (29) indicating a completion of generation of a series of expected values for said second block (3) to said algorithmic pattern generate means (l5).
Claim 8
Dependent Claim
157 words
A memory test apparatus comprising: means (l5) for generating an algorithmic pattern to be inputted to a first block (2) of a memory under test (l); auxiliary pattern generate means (l6) for storing an output from said algorithmic pattern generate means (l5) and for outputting an expected value for a second block (3) of the memory (l) at a preset timing based on the stored output; means (l7) for comparing outputs from said first and second blocks (2, 3) of the memory (l) with expected values for said first and second blocks (2, 3), respectively; memory means for storing an output from said compare means (l7); master timing generate means (l3) for outputting a clock (l3, l4) used to test said first block (2) to said algorithmic pattern generate means (l5); and slave timing generate means (l4) for outputting a slave phase signal (9) to test said second block (3) to said auxiliary pattern generate means (l6).
Claim 9
Dependent Claim
157 words
A memory test apparatus comprising: means (l5) for generating an algorithmic pattern to be inputted to a first block (2) of a memory under test (l); auxiliary pattern generate means (l6) for storing an output from said algorithmic pattern generate means (l5) and for outputting an expected value for a second block (3) of the memory (l) at a preset timing based on the stored output; means (l7) for comparing outputs from said first and second blocks (2, 3) of the memory (l) with expected values for said first and second blocks (2, 3), respectively; memory means for storing an output from said compare means (l7); master timing generate means (l3) for outputting a clock (l3, l4) used to test said first block (2) to said algorithmic pattern generate means (l5); and slave timing generate means (l4) for outputting a slave phase signal (9) to test said second block (3) to said auxiliary pattern generate means (l6).
Claim 10
Dependent Claim
56 words
A memory test apparatus according to Claim 7, wherein said auxiliary pattern generate means (l6) contains a content equal to a content of said first block (2) of the memory under test (l) and outputs as an expected value a pattern identical to a pattern transferred from said first block (2) to said second block (3).
Claim 11
Dependent Claim
21 words
A memory test apparatus according to Claim 7, wherein said second block (3) of the memory (l) is a shift register.
Claim 12
Dependent Claim
46 words
l0. A memory test apparatus according to Claim 7, wherein said auxiliary pattern generate means (l6) receives an address signal and an input data outputted from said algorithmic pattern generate means (l5) and includes a plurality of pattern memory units (33-35) for storing the input data.
Claim 13
Dependent Claim
23 words
A memory test apparatus according to Claim l0, wherein said address signal comprises an X address signal and a Y address signal (6).
Claim 14
Dependent Claim
83 words
A memory test apparatus according to Claim 7, wherein said auxiliary pattern generate means (l6) receives an address signal and an input data outputted from said algorithmic pattern generate means (l5), outputs a fail memory address signal (26) to a memory (20) in which the output from said compare means (l7) is stored, and outputs a generation completion signal (29) indicating a completion of generation of a series of expected values for said second block (3) to said algorithmic pattern generate means (l5).
Claim 15
Dependent Claim
56 words
A memory test apparatus according to Claim 7, wherein said master timing generate means (l3) comprises: a test cycle counter (l00) and a phase counter (l30) each for receiving a basic clock (l02) from an oscillator (l) and a latch (lll) for receiving a timing select signal (3l) outputted from said algorithmic pattern generate means (l5).
Claim 16
Dependent Claim
55 words
A memory test means according to Claim 7, wherein said slave timing generate means (l4) comprises: a phase counter (l30) for receiving a basic clock (l02) from an oscillator (l′) and an OR gate (220) and a flip-flop circuit (260) each for receiving a slave control signal (l05) from said measter timing generate means (l3).
Claim 17
Dependent Claim
61 words
A memory test apparatus according to Claim 7 further comprising at least a second slave timing generate means (l4a-l4f) in addition to said slave timing generate means (l4) wherein: slave control signals (l05a-l05c) from said master timing generate means (l3, l3a) are inputted to said slave timing generate means (l4) and said at least a second slave timing generate means (l4a-l4b).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.