Electrostatic discharge protection devices for integrated circuits

Claim 2

An electrostatic discharge (ESD) protection device for an integrated circuit, having an output buffer stage coupling said circuit to an output pad, comprising: means, coupled to said output pad, for channeling an ESD into said pad away from said output buffer stage, having a turn-on voltage which is less than a voltage which will damage said output buffer stage, whereby said circuit is protected from an ESD into said pad.

Claim 3

The device as set forth in claim 1, wherein said turn-on voltage is a punch-through voltage level for said means for channeling.

Claim 4

The device as set forth in claim 2, wherein said means further comprises: a well-embedded source and well-embedded drain, field effect transistor.

Claim 5

The device as set forth in claim 3, wherein said transistor further comprises: a substrate, having a conductivity of a first type; a first well region in said substrate, having a conductivity of a second type; a first terminal region in said first well region, having a conductivity of said second type of a higher doping concentration than said first well region; a second well region in said substrate, having a conductivity of said second type; a second terminal region in said second well re­gion, having a conductivity of said second type of a higher doping concentration than said second well region; a channel region in said substrate, separating said first well region and said second well region; an insulator layer superposing said substrate; and a gate region superposing said insulator layer over said channel region.

Claim 6

The device as set forth in claim 4, wherein said insulator layer further comprises: a gate dielectric layer, having relatively thin portions over said first and second terminal regions and a relatively thick portion over said channel region.

Claim 7

The device as set forth in claim 5, further comprising: a doped region of said first conductivity type in said channel region, having a higher doping concentration than said substrate.

Claim 8

The device as set forth in claim 2, wherein said integrated circuit has a back bias voltage level, said device further comprising: a punch-through turn-on voltage approximately double that as in a circuit having no said back bias voltage level.

Claim 9

An electrostatic discharge (ESD) protection compo­nent for an integrated circuit, having an output pad, comprising: a substrate, having a conductivity of a first type; a first region in said substrate, having a conduc­tivity of a second type; a first terminal region in said first region, having a conductivity of said second type of a higher doping concentration than said first region; a second region in said substrate, having a conduc­tivity of said second type; a second terminal region in said second region, having a conductivity of said second type of a higher doping concentration than said second region; a channel region in said substrate, separating said first region and said second region; an insulator layer superposing said substrate; and a gate region superposing said thick portion of said insulator layer.

Claim 10

An electrostatic discharge (ESD) protection compo­nent for an integrated circuit, having an output pad, comprising: a substrate, having a conductivity of a first type; a first region in said substrate, having a conduc­tivity of a second type; a first terminal region in said first region, having a conductivity of said second type of a higher doping concentration than said first region; a second region in said substrate, having a conduc­tivity of said second type; a second terminal region in said second region, having a conductivity of said second type of a higher doping concentration than said second region; a channel region in said substrate, separating said first region and said second region; an insulator layer superposing said substrate; and a gate region superposing said thick portion of said insulator layer.

Claim 11

The component as set forth in claim 8, wherein said insulator layer further comprises: a gate dielectric having relatively thin portions over said first and second terminal regions and a relatively thick portion over said channel region.

Claim 12

The component as set forth in claim 8, wherein said gate region and one of said terminal regions are coupled to said output pad and the other of said terminal regions is coupled to a reference potential of said integrated circuit.

Claim 13

The component as set forth in claim 8, wherein said channel region has a first region to second region dimension which induces punch-through turn-on during an ESD occurance but inhibits turn-on during circuit output operation.

Claim 14

An improved electrostatic protection device for a semiconductor substrate integrated circuit, having at least two reference potential levels, an output pad, a first n-­channel transistor, having a drain terminal coupled to the more positive of said reference potential levels, a source terminal coupled to said output pad, and a gate terminal coupled to an output of said circuit, and a second n-channel transistor, having a drain terminal coupled to said output pad, a source terminal coupled to the more negative of said reference potential levels, and a gate terminal coupled to an output of said circuit, characterized by: at least one n-well, n-channel transistor, having a drain terminal coupled to said output pad, a source terminal coupled to said more negative of said reference potential levels, and a semiconductor material gate coupled to said output pad.

Claim 15

An improved electrostatic protection device for a semiconductor substrate integrated circuit, having at least two reference potential levels, an output pad, a first n-­channel transistor, having a drain terminal coupled to the more positive of said reference potential levels, a source terminal coupled to said output pad, and a gate terminal coupled to an output of said circuit, and a second n-channel transistor, having a drain terminal coupled to said output pad, a source terminal coupled to the more negative of said reference potential levels, and a gate terminal coupled to an output of said circuit, characterized by: at least one n-well, n-channel transistor, having a drain terminal coupled to said output pad, a source terminal coupled to said more negative of said reference potential levels, and a semiconductor material gate coupled to said output pad.

Claim 16

The device as set forth in claim 12, wherein said n-well, n-channel transistor further comprises: a channel region having an n-well to n-well dimen­sion which induces punch-through turn-on of said n-well, n-­channel transistor during an ESD into said pad but inhibits turn-on of said transistor during normal circuit output operation.

Claim 17

The device as set forth in claim 13, further comprising: a plurality of n-well contact regions, subjacent each drain contact of said n-channel transistors to said pad.

Claim 18

The device as set forth in claim 14, wherein said contacts further comprise: n+ doped regions in said n-well contact regions.

Claim 19

The device as set forth in claim 13, wherein said channel region further comprises a region doped with carriers of the same conduc­tivity type as said substrate is doped, having a higher doping concentration than said substrate.

Claim 20

An ESD protection semiconductor device for a CMOS integrated circuit, having an output pad and a reference potential Vss, comprising: an n-well, n-channel FET, having a semiconductor gate isolated from a channel region by a relatively thick field dielectric layer, said gate and a drain coupled between said output pad and said circuit and a source coupled to said Vss, such that said FET turns on at a voltage with forces said FET into a punch-through mode during an ESD occurrence into said pad.

Claim 21

An ESD protection semiconductor device for a CMOS integrated circuit, having an output pad and a reference potential Vss, comprising: an n-well, n-channel FET, having a semiconductor gate isolated from a channel region by a relatively thick field dielectric layer, said gate and a drain coupled between said output pad and said circuit and a source coupled to said Vss, such that said FET turns on at a voltage with forces said FET into a punch-through mode during an ESD occurrence into said pad.

Claim 22

The device as set forth in claim 17, said integrated circuit also having a back bias voltage, wherein said punch-through mode occurs at approximately twice the voltage of a circuit not having said back bias.