Generating addresses for circuit units

Claim 3

A method as claimed in Claim 1 characterised in that the address generation signal modification step comprises interrupting the transmission of the address generation signal along the path in such a manner that the interrruption is sequentially effected at successive coupling points along the path.

Claim 4

A method as claimed in Claim 1 or Claim 2 characterised in that the method comprises arranging each circuit unit to modify the address generation signal at regular intervals or at intervals dependent on the nature of the address generation signal, causing each circuit unit to detect whether a previous circuit unit nearer to the end of the path from which the address generation signal is transmitted has modified the address generation signal, and preventing each circuit unit which has detected that no previous unit has modified the address generation signal from subsequently modifying the address generation signal.

Claim 7

A method as claimed in Claim 4 or Claim 5 in which each circuit unit includes an address generator characterised in that the address generator of each unit is arranged to count the pulses or sets of pulses present at its coupling point either until or from a time dependent on the instant when the circuit unit has detected that no previous circuit unit has modified the address generation signal, the address allocated to each unit being dependent on the count contained in the address generator.

Claim 8

A method as claimed in Claim 1 characterised in that the address generation signal comprises one or more level transitions or one or more pulses, that each circuit unit modifies the address generation signal by adding one or more level transitions or pulses to the address generation signal arriving at the coupling point to which that circuit unit is coupled, and that each circuit unit is provided with an address generator which counts the number of level transitions or pulses received at its coupling point and adopts an address dependent on the number counted.

Claim 9

A method as claimed in Claim 7 characterised in that the one or more level transitions or pulses modulate a carrier signal, that each circuit unit demodulates the signal received at its coupling point, modifies the demodulated signal by adding one or more level transitions or pulses, re-modulates the modified signal and applies the remodulated signal to the path, and that each circuit unit is provided with an address generator which counts the number of level transitions or pulses in the demodulated signal and adopts an address dependent on the number counted.

Claim 11

A circuit arrangement for generating a unique address for each of a plurality of circuit units, said circuit arrangement comprising a plurality of circuit units coupled to a single path at individual spaced coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, from which address generation signal each circuit unit derives a unique address, wherein each circuit unit includes an address generator, characterised in that each circuit unit further includes modifying means for modifying the address generation signal at its coupling point, monitoring means for determining whether a circuit unit having a coupling point nearer to said one end has modified the address generation signal and producing an output signal dependent thereon, inhibiting means for inhibiting the action of the modifying means in response to the output signal from the monitoring means, and controlling means for controlling the address generator in response to modified and unmodified address generation signals present at the coupling point.

Claim 12

A circuit arrangement for generating a unique address for each of a plurality of circuit units, said circuit arrangement comprising a plurality of circuit units coupled to a single path at individual spaced coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, from which address generation signal each circuit unit derives a unique address, wherein each circuit unit includes an address generator, characterised in that each circuit unit further includes modifying means for modifying the address generation signal at its coupling point, monitoring means for determining whether a circuit unit having a coupling point nearer to said one end has modified the address generation signal and producing an output signal dependent thereon, inhibiting means for inhibiting the action of the modifying means in response to the output signal from the monitoring means, and controlling means for controlling the address generator in response to modified and unmodified address generation signals present at the coupling point.

Claim 13

A circuit arrangement as claimed in Claim 10, characterised in that the address generation signal comprises a plurality of pulses or sets of pulses or a carrier signal modulated by said pulses or sets of pulses and that the modifying means is operative for intervals which start a given time after the commencement of each pulse or set of pulses and which end before the commencement of the next pulse or set of pulses.

Claim 14

A circuit arrangement as claimed in Claim 11, characterised in that the address generation signal comprises a plurality of pulse pairs.

Claim 15

A circuit arrangement as claimed in any of Claims 10 to 12, characterised in that the modifying means comprises means for interrupting the passage of the address generation signal along the path.

Claim 16

A circuit arrangement as claimed in Claim 11, Claim 12, or Claim 13 when dependent on Claim 12 or Claim 13 characterised in that the address generator in each circuit unit comprises a binary counter which is incremented or decremented by the pulses or sets of pulses of the address generation signal until or from an instant dependent on the output signal from the monitoring means.

Claim 17

A circuit arrangement as claimed in Claim 13 or Claim 14 when dependent on Claim 13, characterised in that the address generator of each circuit unit is coupled to the path at a first point nearer to the control circuit than a second point at which the modifying means of that circuit unit is connected.

Claim 18

A circuit unit as claimed in Claim 15, characterised in that a delay element is coupled in the path between the first and second points.

Claim 19

A circuit arrangement as claimed in Claim 12 and either Claim 13 or Claim 14 when dependent on Claim 14, characterised in that the interrupting means is effective to interrupt the path for a period which starts between the end of the first and the start of the second pulse and ends after the end of the second pulse of each pulse pair.

Claim 20

A circuit arrangement as claimed in Claim 11 or in any of Claims 12 to 17 when dependent on Claim 11, characterised in that the controlling means comprises a bistable circuit set to a desired state in response to a signal from the monitoring means, the output of the bistable circuit being coupled to the address generator to prevent the address generator from responding to further pulses received from the path.

Claim 21

A circuit arrangement as claimed in any of Claims 10 to 18, characterised in that the single path is a transmission line.

Claim 22

A circuit arrangement as claimed in Claim 19, characterised in that the transmission line is an electrical transmission line terminated by its characteristic impedance.

Claim 23

A circuit arrangement as claimed in Claim 20 when dependent on Claim 13, characterised in that said interrupting means comprises means for short circuiting the transmission line.

Claim 24

A circuit arrangment as claimed in Claim 21, characterised in that said monitoring means comprises means for detecting a current flowing in the short circuit.

Claim 25

A circuit arrangement as claimed in Claim 20 when dependent on Claim 13, characterised in that said interrupting means comprises means for open circuiting said transmission line.

Claim 26

A circuit arrangement as claimed in Claim 23, characterised in that said means for open circuiting said transmission line further comprises means for terminating the open circuited section of the transmission line with its characteristic impedance.

Claim 27

A circuit arrangement as claimed in any of Claims 10 to 24, characterised in that the control circuit is arranged to transmit a reset signal along said common path and that each circuit unit further comprises detecting means for detecting said reset signal and producing an output signal for resetting the address generator.

Claim 28

A circuit arrangement for generating a unique address for each of a plurality of circuit units, said circuit arrangement comprising a plurality of circuit units coupled to a single path at individual spaced coupling points along its length and a control circuit for transmitting an address generation signal along the path from one end thereof, wherein each circuit unit includes an address generator, characterised in that the address generation signal comprises one or more signal level transitions or pulses or a carrier signal modulated by said one or more signal level transitions or pulses and that each circuit unit includes modifying means for modifying the address generation signal received at its coupling point by adding one or more further level transitions or pulses to the received signal, means for applying the modified signal to the path for transmission along said path to a succeeding coupling point, and means for applying the received signal to the address generator so that the circuit unit adopts an address dependent on the number of level transitions or pulses received at its coupling point.

Claim 29

A circuit arrangement for generating a unique address for each of a plurality of circuit units, said circuit arrangement comprising a plurality of circuit units coupled to a single path at individual spaced coupling points along its length and a control circuit for transmitting an address generation signal along the path from one end thereof, wherein each circuit unit includes an address generator, characterised in that the address generation signal comprises one or more signal level transitions or pulses or a carrier signal modulated by said one or more signal level transitions or pulses and that each circuit unit includes modifying means for modifying the address generation signal received at its coupling point by adding one or more further level transitions or pulses to the received signal, means for applying the modified signal to the path for transmission along said path to a succeeding coupling point, and means for applying the received signal to the address generator so that the circuit unit adopts an address dependent on the number of level transitions or pulses received at its coupling point.

Claim 30

An arrangement as claimed in Claim 26, characterised in that the address generator comprises a binary counter which counts the number of level transitions or pulses received and whose state is adopted as the address of the circuit unit.

Claim 31

An arrangement as claimed in Claim 26 or Claim 27, characterised in that the control circuit is arranged to transmit a reset signal and that each circuit unit includes detecting means for detecting the reset signal and producing an output signal which is effective to reset the address generator to an initial state.

Claim 32

An arrangement as claimed in any of Claims 10 to 28, characterised in that the address generation signal comprises a carrier signal modulated by one or level transitions or pulses or a plurality of pulses or sets of pulses, that each circuit unit includes a demodulator for demodulating the demodulated carrier signal present at its coupling point, means for modifying the demodulated signal, means for remodulating the modified signal, means for applying the remodulated signal to the path for transmission to succeeding circuit units and means for deriving its address from the demodulated signals.

Claim 33

An arrangement as claimed in Claim 29, characterised in that each circuit unit includes a radio receiver and a radio transmitter, that each radio transmitter is arranged to transmit a signal only to one receiver and that the single path comprises the transmitters and receivers and paths therebetween.

Claim 34

A circuit unit suitable for use in a circuit arrangement as claimed in any of Claims 10 to 30, said circuit unit comprising an input for connection to said coupling point and an address generator coupled to said input, the state of the address generator being modified in response to address generation signals applied to said input characterised in that said circuit unit further comprises modifying means for modifying the address generation signal applied to said input and output means for applying the modified address generation signal to said coupling point.

Claim 35

A circuit unit suitable for use in a circuit arrangement as claimed in any of Claims 10 to 25, said circuit unit comprising an input for connection to said coupling unit, and an address generator coupled to said input, the state of the address generator being modified in response to address generation signals applied to said input characterised in that said circuit unit further comprises modifying means for modifying the address generation signal applied to said input, output means for applying the modified address generation signal to the coupling point, monitoring means for determining whether a modified address generation signal has been applied to said input and producing an output dependent thereon, inhibiting means for inhibiting the action of the modifying means in response to the output of the monitoring means, and controlling means for controlling the address generator in response to the modified and unmodified address generation signals present at said input.

Claim 36

A circuit unit suitable for use in a circuit arrangement as claimed in any of Claims 26 to 30, said circuit unit comprising an input for connection to said coupling point and an address generator coupled to said input, the state of the address generator being modified in response to address generation signals applied to said input characterised in that said circuit unit further comprises modifying means for modifying the address generation signal applied to said input, and output means for applying the modified address generation signal to the coupling point, wherein the modifying means comprises means for adding one or more level transitions or pulses to the address generation signal applied to said input, the address generator comprises a counter which counts the number of level transitions or pulses applied to said input, and the circuit unit further comprises adopting means to enable the circuit unit to adopt the state of the counter as its address.

Claim 37

A circuit unit as claimed in any of Claims 31 to 33, characterised in that the circuit unit further comprises reset detection means for detecting a reset signal applied to said input and producing an output in response to the detection of said reset signal and means for applying the output of the reset detection means to the address generator to reset the address generator to an initial state.

Claim 38

A circuit unit as claimed in any of Claims 31 to 34 for use when the address generation signal comprises a carrier signal modulated by one or more level transitions or pulses or a plurality of pulses or sets of pulses characterised in that the circuit unit further comprises a demodulator coupled to said input, the demodulated output being coupled to said address generator and said modifying means, a modulator for modulating a carrier signal by the modified demodulated signal and means for applying the output of the modulator to the output means.