Full chip integrated circuit tester

Claim 3

A system according to claim 1 characterized by target evaluating means (8) for viewing said luminescent target means (7) and for processing luminescent values at selected test points (3) to develop test values as a func­tion of luminescent values.

Claim 7

A testing method for an integrated circuit chip-to-test (1), characterized by equipping each integrated circuit to be placed under test with a number of conductive test points (3), at identifiable locations accessible by photons even though covered with a passivation layer (15), the passivation layer (15) being dimensioned and selected of material which is photon trans­missive and susceptible to photon assisted tunneling when activated by laser light; adding a thin conductive overlayer (13) over the passivation layer (15), said thin conductive overlayer being metallic or otherwise electrically conductive while penetrable by photons; placing luminescent target means (7) adjacent to the thin conductive overlayer (13) of the integrated circuit 1 under test, to luminesce as a composite function of the laser light activation of the test points (3) and the instanta­neous voltage at such test points (3); connecting pulsed laser means, for activating selected test points (3) on the chip-to-test (1) so as to excite lumi­nescence at values related to the instantaneous voltage potential at the accessed test point; connecting integrated circuit test exercise control means (4) to the chip-to-test (1) to cause electronic activity in the chip-to-test (1) appropriate to the desired test, so as to provide at test points (3) voltage potentials related to operation, whether correct or faulty; placing target evaluation means (8) in position for viewing the luminescent target and processing luminescence values as a function of control values so as to determine test values for the chip-to-test (1).

Claim 8

A testing method for an integrated circuit chip-to-test (1), characterized by equipping each integrated circuit to be placed under test with a number of conductive test points (3), at identifiable locations accessible by photons even though covered with a passivation layer (15), the passivation layer (15) being dimensioned and selected of material which is photon trans­missive and susceptible to photon assisted tunneling when activated by laser light; adding a thin conductive overlayer (13) over the passivation layer (15), said thin conductive overlayer being metallic or otherwise electrically conductive while penetrable by photons; placing luminescent target means (7) adjacent to the thin conductive overlayer (13) of the integrated circuit 1 under test, to luminesce as a composite function of the laser light activation of the test points (3) and the instanta­neous voltage at such test points (3); connecting pulsed laser means, for activating selected test points (3) on the chip-to-test (1) so as to excite lumi­nescence at values related to the instantaneous voltage potential at the accessed test point; connecting integrated circuit test exercise control means (4) to the chip-to-test (1) to cause electronic activity in the chip-to-test (1) appropriate to the desired test, so as to provide at test points (3) voltage potentials related to operation, whether correct or faulty; placing target evaluation means (8) in position for viewing the luminescent target and processing luminescence values as a function of control values so as to determine test values for the chip-to-test (1).

Claim 9

A testing method according to claim 6 for dynamic testing of an integrated circuit chip-to-test (1) before passivation, said chip-to-test (1) having a number of operational circuits and input/output connections, whereby a plurality of test points (3) are connected to said operatio­nal circuits, characterized by placing the chip-to-test (1) in a vacuum environment in a mounting (2) having electrical connections complementary to the input/output connections of the chip-to-test (1), and supporting the chip-to-test (1) for accessibility by laser (5) photons to the test points (3); connecting input/output exercise means (4) to the chip-to-­test (1), so as to exercise the circuits on the chip-to-test (1) in a predetermined pattern, to cause electronic activity in the chip-to-test (1) appropriate to the desired test, so as to provide at the selected test point (3) a voltage potential related to operation, whereby the test point (3) accessed by the pulsed laser (5) provides differing values of electron currents as a function of operation voltage differences; control means (4) connected to said laser so as to excite photoemission from selected test points (3), which photoemis­sion occurs as electron currents at values related to the instantaneous voltage at the accessed test point (3); placing luminescent target means (7) adjacent to the chip-­to-test (1), so as to convert to luminescence of significant duration the photoemission which is a composite function of laser light excitation and of the voltage of the test points, via the passivation layers (15); and evaluating the luminescence to provide test data related to chip (1) operational values.

Claim 10

A testing method according to claim 6 for dynamic testing of an integrated circuit chip-to-test (1) after passivation, characterized by the test point (3) accessed by the pulsed laser (5) pro­viding via photon assisted tunneling through the passivating layer to the conductive layer differing values of electron currents as a function of operation voltage differences.

Claim 11

A testing method according to Claim 7, characterized by connecting bias means (11) adjacent to the integrated circuit (1) under test, thus controlling the threshold for photoemission; whereby the test point (3) activated by the pulsed laser (5) provides significantly differing readings for proper opera­tion and for faulty operations.

Claim 12

A testing method according to Claim 8, further charac­terized by connecting bias means (14) to the thin conductive overlayer (13) of the integrated circuit (1) under test, thus con­trolling the threshold voltage for photon assisted tun­neling; whereby the test point (3) activated by the pulsed laser (5) provides significantly differing readings for proper opera­tion and for faulty operations.

Claim 13

A testing method according to Claim 6, characterized in that the chip-to-test (1) has luminescent target means (7) arrayed over said test points (3) in a fashion whereby relatively long duration luminescence is activated as a composite function of a laser pulse and instantaneous voltage on the respectively related test point (3).

Claim 14

A test method according to claims 8 and 10, charac­terized by equipping said test points (3) with a biased metallic overlayer (13), over said luminescent target means (7), thin enough to be penetrable by a laser activation pulse and also by a fraction of emitted luminescense.