Removable sidewall spacer for lightly doped drain formation using two mask levels

Claim 2

A process for forming lightly doped drains (LDD) (28,36) on devices (10,12) in MOS integrated circuits comprising: forming gates (18,20) for MOS devices (10,12) on an integrated circuit substrate (14,16); forming disposable sidewall spacers (24) along the gate (18,20) spacer edges, the sidewall spacers (24) in turn having edges; forming a first disposable barrier (26) covering first selected gates (18,20); implanting heavily doped source/drain regions (30,38) along the sidewall spacer (24) edges of second selected gates (18,20), while the first selected gates (18,20) are protected by the first disposable barrier (26); removing the disposable sidewall spacers (24) from along the edges of the second selected gates (18,20); selectively implanting LDD regions (28,36) along the second selected gate (18,20) edges; removing the first disposable barrier (26); removing the disposable sidewall spacers (24) from along the edges of the first selected gates (18,20); driving in the source/drain regions (28,30,36,38) along the edges of the second selected gates (18,20) in a first thermal drive-in cycle; reforming the disposable removable sidewall spacers (24) along all of the gate (18,20) edges; forming a second disposable barrier (32) over the second selected gates (18,20); implanting heavily doped source/drain regions (30,38) along the sidewall spacer (24) edges of the first selected gates (18,20) while the second selected gates (18,20) are protected by a second disposable barrier (32); removing the disposable sidewall spacers (24) from along the edges of the first selected gates (18,20); selectively implanting LDD regions (28,36) along the first selected gate (18,20) edges; removing the second disposable barrier (32); removing the disposable sidewall spacers (24) from along the edges of the second selected gates (18,20); and driving in the source/drain regions (28,30,36,38) along the gate edges of the first selected gates (18,20) in a second thermal drive-in step.

Claim 3

A MOS integrated circuit formed by the process of claim 1.

Claim 4

The process of claim 1 in which only two mask levels are employed in the formation of the LDDs (28,36).

Claim 5

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit comprising: forming gates (18,20) for NMOS (10) and PMOS (12) devices on an integrated circuit substrate (14,16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; forming a first removable barrier material (26) over gates (18,20) of a first conductivity type; implanting heavily doped source/drain regions (30,38) along sidewall spacer (24) edges of gates (18,20) of a second conductivity type while gates (18,20) of the first conductivity type are protected by a first removable barrier material (26); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type while the gates (18,20) of the first conductivity type are protected by the first removable barrier material (26); removing the first barrier material (26); driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a first thermal drive-in cycle; reforming the disposable, cleanly removable sidewall spacers (24) around all of the gate (18,20) edges; forming a second removable barrier material (32) over the gates (18,20) of the second conductivity type; implanting heavily doped source/drain regions (30,38) sidewall spacer (24) edges of gates (18,20) of the first conductivity type while gates (18,20) of the second conductivity type are protected by a second removable barrier material (32); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of the first conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the first conductivity type while the gates (18,20) of the second conductivity type remain protected by the second removable barrier material (32); removing the second barrier material (32); removing the disposable sidewall spacer (24) from along the gate (18,20) edges of the second conductivity; and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 6

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit comprising: forming gates (18,20) for NMOS (10) and PMOS (12) devices on an integrated circuit substrate (14,16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; forming a first removable barrier material (26) over gates (18,20) of a first conductivity type; implanting heavily doped source/drain regions (30,38) along sidewall spacer (24) edges of gates (18,20) of a second conductivity type while gates (18,20) of the first conductivity type are protected by a first removable barrier material (26); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type while the gates (18,20) of the first conductivity type are protected by the first removable barrier material (26); removing the first barrier material (26); driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a first thermal drive-in cycle; reforming the disposable, cleanly removable sidewall spacers (24) around all of the gate (18,20) edges; forming a second removable barrier material (32) over the gates (18,20) of the second conductivity type; implanting heavily doped source/drain regions (30,38) sidewall spacer (24) edges of gates (18,20) of the first conductivity type while gates (18,20) of the second conductivity type are protected by a second removable barrier material (32); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of the first conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the first conductivity type while the gates (18,20) of the second conductivity type remain protected by the second removable barrier material (32); removing the second barrier material (32); removing the disposable sidewall spacer (24) from along the gate (18,20) edges of the second conductivity; and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 7

A MOS integrated circuit formed by the process described in claim 4.

Claim 8

The process of claim 4 in which only two mask levels are employed in forming the LDDs (28,36).

Claim 9

A process for forming lightly doped drains (LDDs) (26,38) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit using two mask levels comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a first photoresist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (30) along the gate (18) edges of the second conductivity type; stripping the first resist mask (26) from the gates (20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle; reforming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a second resist mask (32) over the gates (18) of the second conductivity type; implanting heavily doped source/drain regions (38) along the edges of the sidewall spacers (24) of gates (20) of the first conductivity type; removing all disposable sidewall spacers (24) from along the gate edges (20) of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; and stripping the second resist mask (32) from the gates (18) of the second conductivity type; removing the remaining disposable sidewall spacers (24); and driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 10

A process for forming lightly doped drains (LDDs) (26,38) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit using two mask levels comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a first photoresist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (30) along the gate (18) edges of the second conductivity type; stripping the first resist mask (26) from the gates (20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle; reforming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a second resist mask (32) over the gates (18) of the second conductivity type; implanting heavily doped source/drain regions (38) along the edges of the sidewall spacers (24) of gates (20) of the first conductivity type; removing all disposable sidewall spacers (24) from along the gate edges (20) of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; and stripping the second resist mask (32) from the gates (18) of the second conductivity type; removing the remaining disposable sidewall spacers (24); and driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 11

A MOS integrated circuit formed by the process of claim 7.

Claim 12

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate edges (18,20); depositing a first resist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (26) along the gate (18) edges of the second conductivity type; stripping the first resist mask (26) from the gates (20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle; reforming disposable, cleanly removable sidewall spacers (24) along all gate edges (18,20); depositing a second resist mask (32) over gates (18) of the second conductivity type; implanting heavily doped source/drain regions (38) along the edges of the sidewall spacers (24) of the first conductivity type; removing the disposable sidewall spacers (24) from along the gate (20) edges of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; stripping the second resist mask (32) from the gates (18) of the second conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 13

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate edges (18,20); depositing a first resist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (26) along the gate (18) edges of the second conductivity type; stripping the first resist mask (26) from the gates (20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle; reforming disposable, cleanly removable sidewall spacers (24) along all gate edges (18,20); depositing a second resist mask (32) over gates (18) of the second conductivity type; implanting heavily doped source/drain regions (38) along the edges of the sidewall spacers (24) of the first conductivity type; removing the disposable sidewall spacers (24) from along the gate (20) edges of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; stripping the second resist mask (32) from the gates (18) of the second conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 14

A MOS integrated circuit made by the process of claim 9.