Bipolar and/or MOS devices fabricated on integrated circuit substrates

Claim 2

An integrated circuit structure characterized by an improved active device thereon having at least one raised polysilicon contact portion with oxide spacers means 88 on the sidewall thereof and a metal silicide layer 110 formed over the top surface of said raised contact portion as well as the top surfaces of adjacent electrode regions of the active device wherein the separations between said raised contact portion and contact means to said adjacent electrode regions are formed by a self-aligning process whereby the spacing between said raised polysilicon contact portion and said adjacent electrode contact means is reduced thereby permitting horizontal shrinkage of said active device.

Claim 3

The structure of claim 1 wherein said metal silicide 110 over said adjacent electrode regions provide conductive paths adjacent said oxide spacer means 88 on the sidewall of said raised polysilicon contact portion leading to said adjacent electrode contact means.

Claim 4

The structure of claim 2 wherein said active device is an MOS device and said raised polysilicon electrode portion comprises a raised gate elec­trode 80 having oxide spacers 88 on the sidewall thereof.

Claim 5

The structure of claim 3 also having construc­ted thereon one or more bipolar devices character­ized by a raised polysilicon emitter contact por­tion (70) to provide high gain and oxide spacer means (88) on the sidewall of said raised polysilicon con­tact portion of said emitter, and base contact means comprising metal silicide conductive portions (110) adjacent oxide spacer means (88) whereby the speed of said bipolar device is enhanced by de­creasing the resistance path between the intrinsic base 48under the emitter and said conductive por­tion of said base contact means.

Claim 6

The structure of claim 2 wherein said adjacent electrode contact means of said active device also comprise raised polysilicon portions and at least a portion of said conductive paths to said adjacent raised polysilicon contact means are respectively located over segments of said adjacent electrode regions between said adjacent raised polysilicon contact means and said oxide spacers (88) on the sidewall of said raised polysilicon contact; a planarizing layer (116) of insulating material is placed over said active device; and said structure is planarized to provide self-aligned openings therethrough at approximately the same height for al of said raised polysilicon contacts; whereby said active device is further characterized by the substantial absence of steps.

Claim 7

The structure of claim 5 wherein said active device is an MOS device, said raised polysilicon electrode portion comprises a raised gate electrode (80) having oxide spacers (88) on the sidewall thereof, and said adjacent raised polysilicon contacts com­prise raised polysilicon source contacts (174) and raised polysilicon drain contacts (176) for the re­spective source and drain regions, whereby said conductive path portions of metal silicide (110) interconnect said source and drain regions with said raised polysilicon source and drain contacts.

Claim 8

The structure of claim 6 also having construc­ted thereon one or more bipolar devices character­ized by a raised polysilicon emitter contact por­tion (70) to provide high gain and oxide spacer means (88) on the sidewall of said raised polysilicon con­tact portion of said emitter, a raised polysilicon collector contact portion (74), and raised polysili­con base contact means (172) in electrical contact with metal silicide conductive portions (110) adja­cent oxide spacer means (88) whereby the provision of all raised electrode contacts provides a planar structure.

Claim 9

The structure of claim 7 wherein said decrease in the resistance between the intrinsic base (48) under emitter region (72) and said raised polysilicon base contact means (174) in said bipolar device re­sults, at least in part, from at least partial elimination of extrinsic base region (96) and re­placement with metal silicide portions (110) thereby increasing the speed of said device.

Claim 10

The improved integrated circuit structure of claim 8 wherein said partial elimination of extrin­sic base region (96) in said bipolar device results in decreased doping migration into said emitter which permits polysilicon emitter area (72) over said intrinsic base (48) to be reduced without reducing the current carrying ability of said emitter to thereby lower the emitter-base capacitance and thereby increase the speed of said device.

Claim 11

The structure of claim 9 wherein the epitaxial layer of silicon in said structure between said raised polysilicon emitter contact portion (70) and a buried collector region (10) is reduced due to the partial elimination of extrinsic base region (96) without reducing the spacing between said buried collector region (10) and the intrinsic base region (48) formed in said epitaxial silicon beneath said emitter (72) whereby the vertical size of said device may be reduced without increasing the base-10 col­lector capacitance.

Claim 12

The structure of claim 1 where said raised silicon contact is formed by depositing a layer of polysilicon on a substrate; doping said polysili­con sufficiently to alter the conductivity to per­mit formation of said electrode contact therefrom; masking said doped polysilicon to define said elec­trode contact; and removing the remainder of said polysilicon.

Claim 13

The structure of claim 1 wherein said oxide spacers on the sidewalls of said raised polysilicon contact are formed by heating said structure suf­ficiently to form a protective oxide layer on the sidewalls of said raised polysilicon contacts; and forming insulating spacers over said protective oxide layer on the sidewalls of said raised elec­trode contact portions by depositing a layer of insulating material over said structure; and remov­ing portions of said insulating material by a reac­tive ion etch which will leave said insulating spacer on the sidewalls of said polysilicon elec­trode contact portion.

Claim 14

The structure of claim 3 constructed by form­ing a gate oxide over at least a portion of the surface of said substrate; removing said gate oxide from the surface of a portion of said substrate; forming a layer of doped polysilicon over said structure; masking said polysilicon to define a gate contact portion and removing the remainder of said polysilicon; forming insulating spacers ad­joining the sidewall of said polysilicon gate con­tact portion; removing gate oxide from further por­tions of said substrate surface to expose portions of said substrate corresponding to said source and drain regions; forming a metal silicide over said raised gate contact portion and said source and drain regions; forming a further layer of an insu­lating material over said structure; and planariz­ing said structure to remove sufficient insulating material to expose the top portion of said raised polysilicon contact portion.

Claim 15

The structure of claim 4 constructed by depos­iting a layer of polysilicon on said substrate; doping said polysilicon sufficiently to alter the conductivity to permit formation of said electrode contacts therefrom; masking said doped polysilicon to define emitter, collector, and gate electrode contact portions; removing the remainder of said polysilicon; forming an insulating spacer adjoining the sidewall of said raised emitter contact portion and an insulating spacer adjoining the sidewall of said raised gate contact portion; and forming con­ductive path portions adjacent said spacers from base, source, and drain regions in said substrate to other electrode contacts to thereby lower the resistance path between said base, source, and drain regions and said electrode contacts.

Claim 16

The process described in Claim 14 wherein said step of forming said raised emitter contact por­tion, said raised collector contact portion, and said raised gate contact portion comprises forming said raised contact portions from a single layer of polysilicon on said substrate.

Claim 17

The process described in claim 15 wherein said step of locating a conductive path portion of an­other electrode contact means adjacent at least one of said spacers comprises forming base contact means having a conductive path portion adjacent the insulating spacer adjoining said raised emitter contact portion; forming a source contact means having a conductive path portion adjacent said insulating spacer adjoining said raised gate por­tion; and forming a drain contact means having a conductive path portion adjacent said insulating spacer adjoining said raised gate portion.

Claim 18

The process described in claim 16 wherein said steps of forming said conductive path portions comprises forming a layer of a conductive metal silicide to provide a lower resistance path to said electrode contact means.

Claim 19

The structure of claim 5 wherein said raised electrodes are formed by depositing a layer of polysilicon on said substrate; doping said poly­silicon sufficiently to alter the conductivity to permit formation of said electrode contacts there­from; masking said doped polysilicon to define said raised polysilicon electrode contacts; and removing the remainder of said polysilicon.

Claim 20

The structure of claim 6 wherein said raised electrode contacts are formed by depositing a layer of polysilicon on a substrate; doping said poly­silicon sufficiently to alter the conductivity to permit formation of said electrode contacts there­from; masking said doped polysilicon to define said raised source, drain, and gate electrode contacts; and removing the remainder of said polysilicon.

Claim 21

The structure of claim 6 formed by depositing a layer of polysilicon on a substrate; doping said polysilicon sufficiently to alter the conductivity to permit formation of said electrode contacts therefrom; masking said doped polysilicon to define said raised source, drain, and gate electrode con­tacts; removing the remainder of said polysilicon; forming oxide spacer means on the sidewall of said raised gate contact portion; forming a metal sili­cide conductive layer on the top of said raised contacts, on the sidewalls of said raised source and drain contacts, and on said substrate over said source and drain regions between said oxide spacer means and said raised source and drain contacts to provide a conductive path therebetween; and forming a layer of insulating material over said structure which has been planarized to expose the upper sur­face of said contacts; to thereby form said im­proved MOS structure characterized by a highly planarized surface with self-aligned contacts.

Claim 22

The structure of claim 7 constructed by form­ing a buried layer in a semiconductor substrate; growing an epitaxial layer of silicon over said buried layer; forming at least one isolation zone in said structure to separate adjoining active devices; forming a gate oxide over at least a portion of the surface of said epitaxial layer; removing said gate oxide from the surface of a portion of said epitaxial layer; forming a sinker in a portion of said epitaxial layer to provide an electrical contact to said buried layer; forming an intrinsic base in one portion of said epitaxial layer separated from said sinker by an isolation zone; forming a layer of doped polysilicon over said structure; masking said polysilicon to define emitter, collector, base, source, drain, and gate contact portions and removing the remainder of said polysilicon; doping exposed portions of said epi­taxial layer to form said source and drain regions; forming oxide spacers adjoining the sidewall of said polysilicon emitter and gate contact portions; removing gate oxide from further portions of said substrate surface to expose portions of said epi­taxial layer corresponding to source and drain regions; forming a metal silicide over said raised polysilicon emitter, collector, base, source, drain, and gate contact portions, said source and drain regions, and said intrinsic base region; forming a layer of an insulating material over said structure; and planarizing said structure to remove sufficient insulating material to expose the top portion of said raised emitter, collector, base, source, drain, and gate contact portions to thereby open up self-aligned contacts to said electrodes.