Patent EP0215455A2 successfully refreshed from Google Patents.
EP0215455A2
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Write circuit for an erasable programmable read only memory device of a microcomputer
Assignee: Fujitsu Ltd
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Filing: 1986-09-12
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Granted: —
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Expires: 2006-09-12
Abstract
Abstract A write circuit for an EPROM device of a microcomputer comprises a first circuit (28) responsive to an external clock signal (WCLK) and machine clock signals (Ø 1 , Ø 2 ) for supplying a clock signal (CLK) to a program counter (23) of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal (WCLK) has a frequency lower than those of the machine clock signals (Ø 1 , 0 2 ) and the clock signal (CLK) has different frequencies during normal and write-in operation modes so that the address produced in the program counter (23) is successively incremented in synchronism with the machine clock signals (Ø 1 , 0 2 ) during the normal operation mode and is successively incremented in synchronism with the external clock signal (WCLK) during the write operation mode, and a second circuit responsive to the machine clock signals and the bit data of a LSB (least significant bit) of the address from the program counter for generating a bit line clock signal (BCLK) for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes.
Inventors
- 👤 Satoru Fujitsu Limited Patent Dpt. Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 08:45
CPC Classifications
G; G11; G11C; G11C7/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/32; G11C17/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
197 words
A write circuit for an erasable programmable read only memory device of a microcomputer, said microcomputer comprising a program counter which operates in synchronism with machine clock signals, said write circuit comprising: a clock generating circuit responsive to an external clock signal(WCLK)and said machine clock signals for supplying a clock signal(CLK)to said program counter so as to successively increment an address produced in said program counter, said external clock signal (WCLK)having a frequency lower than frequencies of said machine clock signals, said clock signal(CLK) having different frequencies during a normal operation mode and a write-in operation mode so that said address produced in said program counter is successively incremented in synchronism with said machine clock signals during the normal operation mode and is successively incremented in synchronism with said external clock signal(WCLK)during the write operation mode; and a bit line clock generating circuit responsive to said machine clock signals and a bit data of a least significant bit of said address from said program counter for generating a bit line clock signal(BCLK) for inhibiting a write-in data from being written into said erasable programmable read only memory device during a time period in which said address changes.
Claim 2
Dependent Claim
197 words
A write circuit for an erasable programmable read only memory device of a microcomputer, said microcomputer comprising a program counter which operates in synchronism with machine clock signals, said write circuit comprising: a clock generating circuit responsive to an external clock signal(WCLK)and said machine clock signals for supplying a clock signal(CLK)to said program counter so as to successively increment an address produced in said program counter, said external clock signal (WCLK)having a frequency lower than frequencies of said machine clock signals, said clock signal(CLK) having different frequencies during a normal operation mode and a write-in operation mode so that said address produced in said program counter is successively incremented in synchronism with said machine clock signals during the normal operation mode and is successively incremented in synchronism with said external clock signal(WCLK)during the write operation mode; and a bit line clock generating circuit responsive to said machine clock signals and a bit data of a least significant bit of said address from said program counter for generating a bit line clock signal(BCLK) for inhibiting a write-in data from being written into said erasable programmable read only memory device during a time period in which said address changes.
Claim 3
Dependent Claim
160 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1 in which said machine clock signals comprise first and second machine clock signals(Ø 1 and ø 2 )having mutually different phases so that pulses thereof do not overlap each other, said clock generating circuit being supplied with a control signal(CNTL2)indicative of whether the operation mode of said erasable programmable read only memory device is the normal operation mode or the write-in operation mode, said clock generating circuit generating said clock signal(CLK)which rises and falls responsive to transitions of said first and second machine clock signals and Ø 2 )when said control signal(CNTL2)indicates the normal operation mode, and generating said clock signal CLK)which undergoes a first transition in response to a transition of said second machine clock signal(ø2)and undergoes a second transition in response to a transition of said first machine clock signal(Ø 1 )only when said external clock signal(WCLK)undergoes a transition.
Claim 4
Dependent Claim
98 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 2 in which said clock generating circuit generates said clock signal(CLK)which rises with a rise in said first machine clock signal (Ø 1 )and falls with a rise in said second machine clock signal (Ø 2 )when said control signal(CNTL2)indicates the normal operation mode, and generates said clock signal(CLK)which falls with a rise in said second machine clock signal (Ø 2 )and rises with a rise in said first machine clock signal (Ø 1 )only when said external clock signal(WCLK)falls.
Claim 5
Dependent Claim
55 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 2 or 3 in which said first and second machine clock signals(Ø 1 and Ø 2 )have a period in the order of several microseconds and said clock signal(CLK)has a period in the order of fifty milliseconds.
Claim 6
Dependent Claim
165 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in any preceding claim in which said machine clock signals comprise first and second machine clock signals(O 1 and ø 2 )having mutually different phases so that pulses thereof do not overlap each other, said bit line clock generating circuit comprising a delay circuit for delaying the bit data of the least significant bit of said address by use of said first and second machine clock signals(Ø 1 and Ø 2 )so as to produce a delayed bit data, an exclusive-OR circuit supplied with the bit data and the delayed bit data of the least significant bit of said address and a NOR circuit supplied with an output signal of said exclusive-OR circuit and a control signal(CNTL2)indicative of whether the operation mode of said erasable programmable read only memory device is the normal operation mode or the write-in operation mode, said NOR circuit producing said bit line clock signal(BCLK).
Claim 7
Dependent Claim
47 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1 in which said clock signal(CLK)has a period which is sufficiently long for writing an information into said erasable programmable read only memory device during the write operation mode.
Claim 8
Dependent Claim
92 words
A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1 which further comprises a word line driver supplied with said address from said program counter for driving a word line of said erasable programmable read only memory device and a bit line driver supplied with said write-in data and said bit line clock signal(BCLK) from said bit line clock generating circuit for driving a bit line of said erasable programmable read only memory device excluding said time period in which said address changes.
References Cited (Backward Citations)
No citation records indexed.
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