Semiconductor memory with improvend data programming time

Abstract

Abstract A semiconductor memory is disclosed which includes a plurality of memory arrays (31 1 -31 4 ) each having a plurality of memory cells arranged in a matrix form with column lines and row lines and a plurality of bit outputs,decoder means (33 1 -33 4 , 34,-34.) responsive to first address signals (A2-A7) to select corresponding memory cells in said memory arrays, a plurality of data write circuits (36,, 37,-36., 37 4 ) coupled to said memory arrays for writing data into corresponding memory arrays, a write circuit selecting circuit (45) responsive to second address signals (A0,A1) to select one of said write circuits - (36,,37,) to write data into a corresponding memory array (31,) and means responsive to a control signal (MW1,MW2) to modify said second address signal - (A0, A1) so as to cause said write circuit selecting circuit (45) to select simultaneously more than one of said memory arrays (31,-31,) so as to write data applied to the memory immediately into the selected arrays, thus allowing a plurality of memory cells indifferent arrays to be programmed simultaneously.

Inventors

• 👤 Hiroshi Iwahashi
• 👤 Masamichi Asano

Bibliographic Details