Patent US1487429A successfully refreshed from Google Patents.
Patent EP0213843A2 successfully refreshed from Google Patents.
EP0213843A2
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EP
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Digital processor control
Assignee: Advanced Micro Devices Inc
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Filing: 1986-08-14
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Granted: —
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Expires: 2006-08-14
Abstract
Abstract A high-speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.
Inventors
- 👤 Brian Case
- 👤 Rod Fleck
- 👤 Cheng Gang Kong
- 👤 Ole Moller
- 👤 Michael Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/468; G06F12/00; G06F12/14; G06F12/1458; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
137 words
A digital processor control providing execution-time storage allocation which cyclically executes instructions each including a plurality of operand portions, comprising; stack means for execution-time generation of storage allocation signals; means responsive to said storage allocation signals and to each of said plurality of instruction operand portions for generating therefrom a plurality of signals each indicative of one of said operand locations; and file means having a plurality of registers each having a location designator responsive to said plurality of operand location signals for reading the contents of said register having a first location designator upon reception of a predetermined one of said operand location signals indicating said first location and for writing the contents of said register having a second location designator upon reception of a predetermined one of said operand location signals indicating said second location.
Claim 2
Dependent Claim
137 words
A digital processor control providing execution-time storage allocation which cyclically executes instructions each including a plurality of operand portions, comprising; stack means for execution-time generation of storage allocation signals; means responsive to said storage allocation signals and to each of said plurality of instruction operand portions for generating therefrom a plurality of signals each indicative of one of said operand locations; and file means having a plurality of registers each having a location designator responsive to said plurality of operand location signals for reading the contents of said register having a first location designator upon reception of a predetermined one of said operand location signals indicating said first location and for writing the contents of said register having a second location designator upon reception of a predetermined one of said operand location signals indicating said second location.
Claim 3
Dependent Claim
139 words
A digital processor control according to claim 1 wherein said plurality of register within said file means includes a first set having contiguous location designators and a second set having contiguous location designators, said first and second set of designators bearing a predetermined numerical relationship with one another, said operand location signal generating means comprises; a plurality of logic circuit means each responsive to said storage allocation signal and to a predetermined portion of a predetermined one of said instruction operand portions for generating a relative location signal; a plurality of summing means each receiving at a first input signals respresentative of a predetermined one of said instruction operand portions and receiving at a second input said relative location signal generated by a predetermined one of said logic circuit means for generating a predetermined one of operand location signals.
Claim 4
Dependent Claim
49 words
A digital processor control according to claim 1 further providing access protection of user-selectable ones of said register within said file means, further including means responsive to said plurality of operand location signals and to signals indicative of said user-selected register access protection for generating a protection violation signal.
Claim 5
Dependent Claim
49 words
A digital processor control according to claim 2 further providing access protection of user-selectable ones of said register within said file means, further including means responsive to said plurality of operand location signals and to signals indicative of said user-selected register access protection for generating a protection violation signal.
Claim 6
Dependent Claim
69 words
A digital processor control according to claim 3 wherein said registers within said file means are divided into a predetermined number of blocks, each block containing a predetermined number of registers having contiguous location designators; and wherein said protection violation signal generation means includes means for storing a plural-bit value .4 indicative of said user-selected access protection, each bit position thereof corresponding to a predetermined one of said blocks.
Claim 7
Dependent Claim
68 words
A digital processor control according to claim 4 wherein said registers within said file means are divided into a predetermined number of blocks, each block containing a predetermined number of registers having contiguous location designators; and wherein said protection violation signal generation means includes means for storing a plural-bit value indicative of said user-selected access protection, each bit position thereof corresponding to a predetermined one of said blocks.
Claim 8
Dependent Claim
23 words
A digital processor control according to claim 1 wherein a predetermined one of said registers within said file means is an indirect pointer.
Claim 9
Dependent Claim
26 words
A digital processor control according to claim 1 wherein said plurality of operand portions comprises a first and second read operand and a first write operand.
Claim 10
Independent Claim
131 words
A method of execution-time storage allocation by a digital processor control which cyclically executes instructions each including a plurality of operand portions, predetermined sequences of said instructions forming a procedure, said control having a file of registers each having a location designator, comprising the steps of: a) setting a stack pointer upon entry to a procedure; b) for each of said operation portions of said instructions within said procedure calculating an effective operand register designation relative to said stack pointer; and c) resetting said stack pointer upon entry to a procedure called by said procedure entered at step (a) so as to provide a predetermined communication overlap between the storage allocated . 4 for the procedure entered in step (a) and the storage allocated for said procedure called by said procedure.
Claim 11
Independent Claim
131 words
A method of execution-time storage allocation by a digital processor control which cyclically executes instructions each including a plurality of operand portions, predetermined sequences of said instructions forming a procedure, said control having a file of registers each having a location designator, comprising the steps of: a) setting a stack pointer upon entry to a procedure; b) for each of said operation portions of said instructions within said procedure calculating an effective operand register designation relative to said stack pointer; and c) resetting said stack pointer upon entry to a procedure called by said procedure entered at step (a) so as to provide a predetermined communication overlap between the storage allocated . 4 for the procedure entered in step (a) and the storage allocated for said procedure called by said procedure.
Claim 12
Dependent Claim
77 words
An execution-time storage allocation method according to claim 9 wherein said file of registers is divided into a predetermined number of blocks, each block containing a predetermined number of registers having contiguous location designators further including the user-selectable register access protection steps of: d) designating ones of said blocks as proscribed-access blocks; e) aborting execution of an instruction having an operand portion with an effective address as calculated at step (b) within one of said proscribed-access blocks.
Claim 13
Dependent Claim
42 words
An execution-time storage allocation method according to claim 10 wherein said digital processor control is capable of performing multiple tasks, further including the step of: f) for each task of said multiple tasks designating mutually-exclusive ones of said blocks as proscribed-access blocks.
Claim 14
Dependent Claim
69 words
An execution-time storage allocation method according to claim 9 wherein said file of registers has a first set of contiguous location designators and a second set of contiguous location designators, said first and second set of designators bearing a predetermined numerical relationship with one another, and wherein step (b) further calls for said calculation of an effective designator within said second set by reference to said predetermined numerical relationship.
References Cited (Backward Citations)
No citation records indexed.
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