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EP0212545A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor memory device having nibble mode function

Assignee: Fujitsu Ltd
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Filing: 1986-08-12
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Granted: —
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Expires: 2006-08-12
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Abstract

Abstract In a semiconductor memory device having a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks; data bus lines are provided separately to each of the first and second cell blocks; sense amplifiers are provided separately to each of data bus lines; a column decoder for connecting between bit lines is provided in the memory cell array and corresponding data bus lines based on address signals and gate signals in selection state; a switching circuit is provided for switching between sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and for connecting these sense amplifiers to output buffers; and a clock signal generating circuit is provided for generating the gate signals, and the gate signals are generated by such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of the column address strobe signal in the nibble mode.

Inventors

  • 👤 Masao Nakano
  • 👤 Yoshihiro Takemae

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 20:36
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/10; G11C7/1015; G11C7/103; G11C7/1033

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 168 words
A semiconductor memory device having a nibble mode function comprising: memory cell arrays divided into two groups of first and second cell blocks, data bus lines provided separately to each of said first and second cell blocks, sense amplifiers provided separately to each of data bus lines, a column decoder for connecting between bit lines provided in said memory cell array and corresponding data bus lines based on address signals and gate signals in a selection state, switching means for switching between sense amplifiers belonging to said first cell block and sense amplifiers belonging to said second cell block and for connecting these sense amplifiers to output buffers, and a clock signal generating means for generating said gate signals, and said gate signals being generated by such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of said column address strobe signal in said nibble mode.
Claim 2
Dependent Claim 168 words
A semiconductor memory device having a nibble mode function comprising: memory cell arrays divided into two groups of first and second cell blocks, data bus lines provided separately to each of said first and second cell blocks, sense amplifiers provided separately to each of data bus lines, a column decoder for connecting between bit lines provided in said memory cell array and corresponding data bus lines based on address signals and gate signals in a selection state, switching means for switching between sense amplifiers belonging to said first cell block and sense amplifiers belonging to said second cell block and for connecting these sense amplifiers to output buffers, and a clock signal generating means for generating said gate signals, and said gate signals being generated by such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of said column address strobe signal in said nibble mode.
Claim 3
Dependent Claim 81 words
A semiconductor memory device having a nibble mode function as claimed in claim 1, wherein said gate signal is raised in response to a first trailing edge of the column address strobe signal only in an initial starting step of the nibble mode, after this step, the leading edge of the column address strobe signal is used for raising the gate signal and the trailing edge of the column address strobe signal for lowering the gate signal as the nibble mode.
Claim 4
Dependent Claim 38 words
A semiconductor memory device having a nibble mode function as claimed in claim 2, wherein said first trailing edge of the column address strobe signal is defined by a first trailing edge of a row address strobe signal.

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