Patent EP0212004A2 successfully refreshed from Google Patents.
EP0212004A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A solid state inverting circuit having a bipolar transistor for rapidly processing I/O signals
Assignee: Toshiba Corp
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Filing: 1985-12-11
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Granted: —
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Expires: 2005-12-11
Abstract
Abstract An improved inverter circuit capable of quickly attaining complete inversion is shown. The circuit comprises bipolar transistors (27, 29) by which an inverted output takes a level near the rated level and MOS transistors (23, 25) by which the inverted output reaches the rated level from the near level. The MOS transistors (23, 25) have large gate region dimensions and are driven by a bipolar transistor (31) which possesses high current driving capacity.
Inventors
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 11:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/0175; H03K19/017509; H03K19/017518
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
An inverter circuit, comprising: an input terminal; and a first bipolar transistor (27) having a collector terminal for connection to a high level voltage source, characterized by: a second bipolar transistor (29) whose collector terminal is connected to said emitter terminal of the first transistor (27) and whose emitter terminal is for connection to a low level voltage source; an output terminal which is connected to said emitter terminal of the first transistor (27); means (23, 25) which is connected to the bases of said bipolar transistors for switching said bipolar transistors (27, 29) in response to the voltage level of said input terminal; a MOS transistor (41, 43) which is provided in parallel to at least one of said bipolar transistors (27, 29); a third bipolar transistor (31) whose emitter is connected to the gate of said MOS transistor (41, 43); and said third bipolar transistor (31)having its base connected to said input terminal, and being switchable depending upon the level of the input signal.
Claim 2
Dependent Claim
166 words
An inverter circuit, comprising: an input terminal; and a first bipolar transistor (27) having a collector terminal for connection to a high level voltage source, characterized by: a second bipolar transistor (29) whose collector terminal is connected to said emitter terminal of the first transistor (27) and whose emitter terminal is for connection to a low level voltage source; an output terminal which is connected to said emitter terminal of the first transistor (27); means (23, 25) which is connected to the bases of said bipolar transistors for switching said bipolar transistors (27, 29) in response to the voltage level of said input terminal; a MOS transistor (41, 43) which is provided in parallel to at least one of said bipolar transistors (27, 29); a third bipolar transistor (31) whose emitter is connected to the gate of said MOS transistor (41, 43); and said third bipolar transistor (31)having its base connected to said input terminal, and being switchable depending upon the level of the input signal.
Claim 3
Dependent Claim
37 words
An inverter circuit of Claim 1, wherein said MOS transistor is a first N-channel transistor (43) whose drain terminal is connected to said output terminal and whose source terminal is connected to said low level voltage source.
Claim 4
Dependent Claim
50 words
An inverter circuit of Claim 1 or 2, wherein the emitter terminal of said third bipolar transistor (31) and the gate terminal of said MOS transistor (43) are connected to said low level voltage source via an N-channel MOS transistor (39) whose gate terminal is connected to said output terminal.
Claim 5
Dependent Claim
50 words
An inverter circuit of Claim 1, 2 or 3 further comprising: a P-channel MOS transistor (41) with its drain terminal connected to said output terminal, its source terminal connected to said high level voltage source, and its gate terminal connected to the emitter terminal of said third bipolar transistor (31).
Claim 6
Dependent Claim
42 words
An inverter circuit of any one of claims 1 to 4, wherein at least one of said IDS transistors (41,43) is connected to the emitter of said third bipolar transistor (31) via at least one of voltage regulating diode (33, 35, 37).
Claim 7
Dependent Claim
97 words
An inverter circuit of Claim 2, wherein said switching means comprises a first P-channel MOS transistor (23) with its source terminal connected to said high level voltage source, its drain terminal connected to the base terminal of said first bipolar transistor (27), and its gate terminal connected to said input terminal, and a second N-channel M OS transistor (25) with its source terminal connected to the base terminal of said second bipolar transistor (29), its drain terminal connected to the collector terminal of said second bipolar transistor (29), and its gate terminal connected to said input terminal.
Claim 8
Dependent Claim
57 words
An inverter circuit of Claim 6, wherein the emitter terminal of said third bipolar transistor (31) and the gate terminal of said first N-channel MOS transistor (41) are connected to said low level voltage source via a third N-channel MOS transistor (39) whose gate terminal is connected to the emitter terminal of said first bipolar transistor (27).
Claim 9
Dependent Claim
46 words
An inverter circuit of claim 7, wherein the base terminal of said second bipolar transistor (29) is connected to said low level voltage source via a fourth N-channel MOS transistor (39) whose gate terminal is connected to the base terminal of said first bipolar transistor (27).
Claim 10
Dependent Claim
39 words
An inverter circuit of Claim 8, wherein the base terminal of said first bipolar transistor (61) is connected to said low.level voltage source via a fifth N-channel MOS transistor (49) whose gate terminal is connected to said input terminal.
Claim 11
Dependent Claim
28 words
An inverter circuit of Claim 2, wherein the emitter terminal of said first bipolar transistor (61) is connected to said output terminal via a voltage lowering diode (63).
Claim 12
Dependent Claim
43 words
An inverter circuit of Claim 9, further comprising: a P-channel MOS transistor (67) whose drain terminal, source terminal, and gate terminal are connected to said output terminal, said high level voltage source, and the emitter terminal of said third bipolar transistor (45) respectively.
References Cited (Backward Citations)
No citation records indexed.
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