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EP0211570A2
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Progressive scan display system with correction for non-standard signals
Assignee: RCA Licensing Corp
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Filing: 1986-07-24
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Granted: —
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Expires: 2006-07-24
Abstract
Abstract In a double scanning receiver including a video speed-up memory with read and write clocks locked to multiples of burst, visible artifacts tend to be produced when displaying non-standard video signals (e.g., from a VCR, gme, computer, etc.) due to skew of the memory clock signals with respect to horizontal sync. Skew artifacts are corrected by delaying (in 95;96,98) the output signal of the memory (50) as a direct function of the read clock skew and as an inverse function of the write clock skew. The write clock skew is measured (410-426,Fig.4) for each memory read and write cycle. The read clock skew (in latch 66) for the first memory read cycle corresponds to the write clock skew (in latch 64) measured at the start of the first read cycle. The read clock skew for the second memory read cycle is obtained by adding to the write clock skew measured at the start of the second read cycle a measured half-line period of the video input signal and taking the fractional part of the sum thereof. The integer part of the sum is detected (68) to initiate the start of the second memory read cycle. The difference (96) between the write skew signal (64) and twice (84) the read skew signal (66) determines the delay imparted to the video signal.
Inventors
- 👤 Russell Thomas Fling
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 10:14
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
313 words
A progressive scan display system comprising: a) signal source means (18,20) for providing a video input signal (S3) of a given line rate, a read clock signal (FR), and a write clock signal (FW), said clock signals tending to exhibit skew when said video input signal is of non-standard form; b) video speed-up memory means (40,42) coupled to said signal source means and including means (50) for storing at least one line of said video input signal during a write cycle of said memory means and means (68,78,57) coupled thereto for performing first and second read cycles of said memory means in providing a video output signal of double said given line rate; c) display means (30) coupled to said memory means and synchronized therewith for displaying said video output signal; and d) skew corrector means (44,46) for generating read and write clock skew indicator signals and for imparting an effective delay to said video output signal as a direct function of said read clock skew indicator signal and as an inverse function of said write clock skew indicator signal during each said read cycle of said memory means for reducing visible artifacts on said display means due to skew of said clock signals; characterised in that said skew corrector means comprises: e) first means (32) coupled to said signal source means for deriving said read and write clock skew indicator signals from said write clock signal and said video input signal; and f) second means (84,86) in said skew corrector means for doubling the value of the derived read clock skew indicating signal for each said read cycle of said memory means and for subtracting therefrom the value of said write clock skew indicating signal of the preceeding write cycle of said memory means to form a control signal (59) for controlling the effective delay (94;96,98) imparted to said video output signal.
Claim 2
Dependent Claim
313 words
A progressive scan display system comprising: a) signal source means (18,20) for providing a video input signal (S3) of a given line rate, a read clock signal (FR), and a write clock signal (FW), said clock signals tending to exhibit skew when said video input signal is of non-standard form; b) video speed-up memory means (40,42) coupled to said signal source means and including means (50) for storing at least one line of said video input signal during a write cycle of said memory means and means (68,78,57) coupled thereto for performing first and second read cycles of said memory means in providing a video output signal of double said given line rate; c) display means (30) coupled to said memory means and synchronized therewith for displaying said video output signal; and d) skew corrector means (44,46) for generating read and write clock skew indicator signals and for imparting an effective delay to said video output signal as a direct function of said read clock skew indicator signal and as an inverse function of said write clock skew indicator signal during each said read cycle of said memory means for reducing visible artifacts on said display means due to skew of said clock signals; characterised in that said skew corrector means comprises: e) first means (32) coupled to said signal source means for deriving said read and write clock skew indicator signals from said write clock signal and said video input signal; and f) second means (84,86) in said skew corrector means for doubling the value of the derived read clock skew indicating signal for each said read cycle of said memory means and for subtracting therefrom the value of said write clock skew indicating signal of the preceeding write cycle of said memory means to form a control signal (59) for controlling the effective delay (94;96,98) imparted to said video output signal.
Claim 3
Dependent Claim
36 words
A system as recited in Claim 1 further comprising third means (68,FF,72) in said skew corrector means responsive to said clock skew indicator signals for initiating (R/W) said read and write cycles of said memory means.
Claim 4
Dependent Claim
41 words
A system as recited in Claim 1 wherein said video output signal comprises a luminance (Y') and a chrominance (C' omponent and wherein said second means includes means (96,98,94) for effectively delaying said components as different functions of said control signal.
Claim 5
Dependent Claim
135 words
A system as recited in Claim 1 wherein: said first means comprises measurement means (404) for providing a primary skew indicating signal (P) representative of skew of said write clock signal at the beginning of each write cycle and each first read cycle of said memory means, and a secondary skew indicating signal (S) representative of skew of said write clock at the beginning of said second memory read cycle; and said second means comprises a first storage means (64) for storing said primary skew indicating signal at the beginning of said write cycle and a second storage means (66) for alternately storing said primary and secondary skew indicating signals at the beginning of said first and second read cycles, respectively, and means (84,86) coupled to said storage means for forming said delay control signal.
Claim 6
Dependent Claim
31 words
A system as recited in Claim 4 further comprising third means (68,78,FF,72) responsive to said primary and secondary skew indicating signals for initiating read and write cycles of said memory means.
Claim 7
Dependent Claim
82 words
A system as recited in Claim 1 wherein said first means includes means (430) for adding to said write clock skew indicating signal (from 422) a signal (T2) representing a half-line period of said video input signal, to form a sum signal having integer and fraction parts, and means (436,442) responsive to an integer part of said sum signal for producing a control pulse, said second means including means (68,78) responsive to said control pulse for initiating said second memory read cycle.
Claim 8
Dependent Claim
67 words
A system as recited in Claim 1 wherein said video output signal comprises a luminance component (Y') and a chrominance (C') component, said delay control signal (S9) comprises a binary signal manifestation, and said second means includes arithmetic means (88,94,92) for rounding off fractional portions of said binary signal manifestation to provide a modified signal manifestation for controlling the effective delay (94) imparted to said chrominance component.
Claim 9
Dependent Claim
196 words
A progressive scan display system comprising a video speed-up memory means (40,42) for doubling the horizontal line rate of a video input signal supplied thereto to provide a double line-rate video output signal (S4,S5) to a display means (30), a source (20) of read and write clock signals (FR,FW) coupled to said memory means for controlling read and write operations thereof, and skew correction means (44,46) for imparting variable delay to said double line-rate video output signal for reducing visible artifacts on said display means caused by skew of said clock signals, characterised in that said skew correction means comprises: first means (402) responsive to said video input signal and said write clock signal for providing a write clock skew indicating signal ('PRIMARY SKEW'); second means (430-436) coupled to the first means for deriving a read clock skew indicating signal from said write clock skew indicating signal; and third means (94;96,98) coupled to said memory means for delaying said video output signal as a function of a difference (86) between said write clock skew indicating signal and a multiple (84) of said read clock skew indicating signal to minimize said visible artifacts on said display means.
Claim 10
Dependent Claim
196 words
A progressive scan display system comprising a video speed-up memory means (40,42) for doubling the horizontal line rate of a video input signal supplied thereto to provide a double line-rate video output signal (S4,S5) to a display means (30), a source (20) of read and write clock signals (FR,FW) coupled to said memory means for controlling read and write operations thereof, and skew correction means (44,46) for imparting variable delay to said double line-rate video output signal for reducing visible artifacts on said display means caused by skew of said clock signals, characterised in that said skew correction means comprises: first means (402) responsive to said video input signal and said write clock signal for providing a write clock skew indicating signal ('PRIMARY SKEW'); second means (430-436) coupled to the first means for deriving a read clock skew indicating signal from said write clock skew indicating signal; and third means (94;96,98) coupled to said memory means for delaying said video output signal as a function of a difference (86) between said write clock skew indicating signal and a multiple (84) of said read clock skew indicating signal to minimize said visible artifacts on said display means.
Claim 11
Dependent Claim
53 words
A display system as recited in Claim 8 wherein said third means includes means (84) for doubling said read clock skew indicating signal and means (86) for subtracting therefrom said write clock skew indicating signal to form a delay control signal, said delay means being responsive thereto for delaying said video output signal.
Claim 12
Dependent Claim
51 words
A display system as recited in Claim 8 wherein said video output signal comprises a luminance component (Y') and a chrominance component (C') and said delay means is responsive to said delay control signal for imparting highe r resolution delays to said luminance component (96,98) than to said chrominance component (94).
Claim 13
Dependent Claim
69 words
A display system as recited in Claim 8 wherein said second means includes means (430) for adding to said write clock skew indicating signal a signal representing a half-line period of said video input signal, to form a sum signal having integer and fractional parts, said fractional part of said sum signal corresponding to said read clock skew indicating signal for each second read cycle of said memory means.
Claim 14
Dependent Claim
87 words
A display system as recited in Claim 8 wherein said video speed-up memory means is of a type in which each write cycle thereof is followed by first and second read cycles and wherein said third means includes a first memory (64) for storing said write skew indicating signal at the start of each said write cycle and a second memory (66) for alternately storing said write skew and said read skew indicating signals at the start of respective ones of said first and second read cycles.
References Cited (Backward Citations)
No citation records indexed.
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