Random access memories

Claim 2

A memory comprising: a plurality of memory cells; a column decoder; a row decoder; first means responsive to an output from each of said column and row decoders for addressing a first one of said memory cells; and second means responsive to a control signal and a plurality of clock pulses for addressing in a predetermined sequence the remainder of said memory cells.

Claim 3

A memory according to claim 1 wherein said plurality of clock pulses comprises a plurality of successive clock pulses and said second means comprises means for addressing the remainder of said memory cells in response to a corresponding number of said successive clock pulses.

Claim 4

A memory comprising: means for addressing in response to an output from a column and a row decoder a first one of a plurality of memory cells in a predetermined sequence; means for addressing in response to a control signal a second one of said cells in said predetermined sequence; means for sequentially addressing in response to said control signal and a corresponding number 6f successive clock pulses each remaining cell in said sequence; and means for sequentially reading to a data output line in response to said control signal and each of said successive clock pulses used for addressing the third and succeeding cells in said sequence the contents of the cells in said sequence.

Claim 5

A memory comprising: means for addressing in response to an output from a column and a row decoder a first one of a plurality of memory cells in a predetermined sequence; means for addressing in response to a control signal a second one of said cells in said predetermined sequence; means for sequentially addressing in response to said control signal and a corresponding number 6f successive clock pulses each remaining cell in said sequence; and means for sequentially reading to a data output line in response to said control signal and each of said successive clock pulses used for addressing the third and succeeding cells in said sequence the contents of the cells in said sequence.

Claim 6

A memory according to claim 3 wherein each of said cells in said sequence comprises an address, and said means for addressing said first cell comprises: means for decoding the address of said first cell by means of a column and a row decoder; means for loading the outputs of said column and row decoders into a pair of column shift registers and a pair of row shift registers having outputs coupled to a first and a second set of said memory cells, respectively, said means for addressing said second cell in said sequence comprises: means for coupling corresponding inputs of said first and said second column shift registers in response to said control signal, said means for sequentially addressing each remaining cell comprises: means for shifting each of said column shift registers alternately in response to alternate ones of said successive clock pulses, respectively; means for shifting each of said row shift registers in response to a predetermined output from a corresponding one of said column shift registers, respectively; and said means for reading the contents of said cells comprises: means for coupling the outputs of said first and said second sets of memory cells to said data output line alternately in response to said alternate ones of said clock pulses, respectively.

Claim 7

A memory having a plurality of memory cells located in a first and a second set of said cells comprising: means for addressing a first cell in said first set of cells; means for setting a multiplexer having a first input coupled to the outputs of said cells in said first set and a second input coupled to the outputs of said cells in said second set to read out to a data register the contents of said first cell in said first set; means for addressing, in response to a control signal a first cell in said second set; means for reading out to a data output line from said data register in response to said control signal and a first clock pulse the contents of said first cell in said first set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the contents of said first cell in said second set; means for addressing in response to said latter clock pulse the cell next in order in said first set; means for reading out to said data output line from said data register -in response to said control signal and the clock pulse next in order the contents of said first cell in said second set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the contents of the cell next in order in said first set; means for addressing in response to said latter clock pulse the cell next in order in said second set; means for reading out to said data output line from said data register in response to said control signal and the clock pulse next in order the contents of said latter cell in said first set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the content of the cell next in order in said second set; means for addressing in response to said latter clock pulse the cell next in order in said first set; and means for reading out to said data output line from said data register in response to said control signal and the clock pulse next in order the contents of said latter cell in said second set.

Claim 8

A memory having a plurality of memory cells located in a first and a second set of said cells comprising: means for addressing a first cell in said first set of cells; means for setting a multiplexer having a first input coupled to the outputs of said cells in said first set and a second input coupled to the outputs of said cells in said second set to read out to a data register the contents of said first cell in said first set; means for addressing, in response to a control signal a first cell in said second set; means for reading out to a data output line from said data register in response to said control signal and a first clock pulse the contents of said first cell in said first set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the contents of said first cell in said second set; means for addressing in response to said latter clock pulse the cell next in order in said first set; means for reading out to said data output line from said data register -in response to said control signal and the clock pulse next in order the contents of said first cell in said second set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the contents of the cell next in order in said first set; means for addressing in response to said latter clock pulse the cell next in order in said second set; means for reading out to said data output line from said data register in response to said control signal and the clock pulse next in order the contents of said latter cell in said first set; means for switching said multiplexer in response to said latter clock pulse to read out to said data register the content of the cell next in order in said second set; means for addressing in response to said latter clock pulse the cell next in order in said first set; and means for reading out to said data output line from said data register in response to said control signal and the clock pulse next in order the contents of said latter cell in said second set.

Claim 9

A memory comprising: a first and a second set of memory cells; a column decoder having a plurality of output lines; a row decoder having a plurality of output lines; a first column shift register having a plurality of input and output lines; a second column shift register having a plurality of input and output lines; a first row shift register having a plurality of input and output lines; a second row shift register having a plurality of input and output lines; a multiplexer having a first input L and a second input R; means coupling each output line of said row decoder to a corresponding row in said first and said second set of memory cells for addressing said row; means coupling a first set of output lines of said column decoder to corresponding inputs of said first column shift register for loading said latter shift register in response to a control signal when said signal has a predetermined first level; means coupling a second set of output lines of said column decoder to corresponding inputs of said second column shift register for loading said latter shift register in response to said control signal when said signal has said predetermined first level; means coupling each output line of said first column shift register to a corresponding column in said first set of memory cells for addressing said latter column; means coupling each output line of said second column shift register to a corresponding column in said second set of memory cells for addressing said latter column; means coupling each output line of said first row shift register to a c rresponding row in said first set of memory cells for addressing said latter row; means coupling each output line of said second row shift register to a corresponding row in said second set of said memory cells for addressing said latter row; means for coupling the outputs of each of said memory cells in said first set to said first input L of said multiplexer; means for coupling the outputs of each of said memory cells in said second set to said second input R of said multiplexer; means which is responsive to said control signal for coupling the outputs of each of said memory cells in said first and said second set to a data output line when said control signal has said first predetermined level; means which is responsive to a control signal for coupling corresponding inputs of said first and said second column shift registers when said control signal has a second predetermined level; first means coupled to said second set of outputs of said column decoder and said multiplexer which is responsive to a control signal for providing a switching signal L/R and a means which is responsive to said control signal and a first clock C K for selectively switching said first and said second inputs L,R of said multiplexer to said data output line when any one of said latter outputs is high and said control signal has said first predetermined level; second means coupled to said multiplexer which is responsive to said control signal and said first clock CK for selectively coupling said first and said second inputs L,R of said multiplexer to said data output line when said control signal has said second predetermined level; means which is responsive ti) said first clock CK for providing a second clock CKL to said first column shift register for shifting said first column shift register from a first column to a second column in said first set of memory cells when said first input L of said multiplexer is coupled to said data output line and said control signal has said second predetermined level; means which is responsive to said first clock CK for providing a third clock CKR to said second column shift register for shifting said second column shift register from a first column to a second column in said second set of memory cells when said second input R of said multiplexer is coupled to said data output line and said control signal has said second predetermined level; means coupling an output of said first column shift register to said first row shift register for shifting said first row shift register from a first row to a second row of memory cells in said first set when said control signal has said second predetermined level and said latter output changes from a first (high) to a second (low) level; and means coupling an output of said second column shift register to said second row shift register for shifting said second row shift register from a first row to a second row of memory cells in said second set when said control signal has said second predetermined level and said latter output changes from said first to said second level.

Claim 10

A memory comprising: a first and a second set of memory cells; a column decoder having a plurality of output lines; a row decoder having a plurality of output lines; a first column shift register having a plurality of input and output lines; a second column shift register having a plurality of input and output lines; a first row shift register having a plurality of input and output lines; a second row shift register having a plurality of input and output lines; a multiplexer having a first input L and a second input R; means coupling each output line of said row decoder to a corresponding row in said first and said second set of memory cells for addressing said row; means coupling a first set of output lines of said column decoder to corresponding inputs of said first column shift register for loading said latter shift register in response to a control signal when said signal has a predetermined first level; means coupling a second set of output lines of said column decoder to corresponding inputs of said second column shift register for loading said latter shift register in response to said control signal when said signal has said predetermined first level; means coupling each output line of said first column shift register to a corresponding column in said first set of memory cells for addressing said latter column; means coupling each output line of said second column shift register to a corresponding column in said second set of memory cells for addressing said latter column; means coupling each output line of said first row shift register to a c rresponding row in said first set of memory cells for addressing said latter row; means coupling each output line of said second row shift register to a corresponding row in said second set of said memory cells for addressing said latter row; means for coupling the outputs of each of said memory cells in said first set to said first input L of said multiplexer; means for coupling the outputs of each of said memory cells in said second set to said second input R of said multiplexer; means which is responsive to said control signal for coupling the outputs of each of said memory cells in said first and said second set to a data output line when said control signal has said first predetermined level; means which is responsive to a control signal for coupling corresponding inputs of said first and said second column shift registers when said control signal has a second predetermined level; first means coupled to said second set of outputs of said column decoder and said multiplexer which is responsive to a control signal for providing a switching signal L/R and a means which is responsive to said control signal and a first clock C K for selectively switching said first and said second inputs L,R of said multiplexer to said data output line when any one of said latter outputs is high and said control signal has said first predetermined level; second means coupled to said multiplexer which is responsive to said control signal and said first clock CK for selectively coupling said first and said second inputs L,R of said multiplexer to said data output line when said control signal has said second predetermined level; means which is responsive ti) said first clock CK for providing a second clock CKL to said first column shift register for shifting said first column shift register from a first column to a second column in said first set of memory cells when said first input L of said multiplexer is coupled to said data output line and said control signal has said second predetermined level; means which is responsive to said first clock CK for providing a third clock CKR to said second column shift register for shifting said second column shift register from a first column to a second column in said second set of memory cells when said second input R of said multiplexer is coupled to said data output line and said control signal has said second predetermined level; means coupling an output of said first column shift register to said first row shift register for shifting said first row shift register from a first row to a second row of memory cells in said first set when said control signal has said second predetermined level and said latter output changes from a first (high) to a second (low) level; and means coupling an output of said second column shift register to said second row shift register for shifting said second row shift register from a first row to a second row of memory cells in said second set when said control signal has said second predetermined level and said latter output changes from said first to said second level.

Claim 13

8 . A method according to claim 7 wherein each of said cells in said sequence comprises an address, said steps of addressing said first cell comprises the steps of: decoding the address of said first cell by means of a column and a row decoder; loading the outputs of said column and row decoders into a pair of column shift registers and a pair of row shift registers having outputs coupled to a first and a second set of said memory cells, respectively, said step of addressing said second cell in said sequence comprises the step of: coupling corresponding inputs of said first and said second column shift registers in response to said control signal, said step of sequentially addressing each remaining cell comprises the steps of: shifting each of said column shift registers alternately in response to alternate ones of said successive clock pulses, respectively; shifting each of said row shift registers in response to a predetermined output from a corresponding one of said column shift registers, respectively; and said step of reading the contents of said cells comprises the step of: coupling the outputs of said first and said second sets of memory cells to said data output line alternately in response to said alternate ones of said clock pulses, respectively.