Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
A master-slave type flip-flop circuit including a normal function in a normal mode by a clock signal for flip-flop operation and a scanning function in a scanning mode by a scanning clock for testing an integrated circuit comprising: a master stage having a first pair of differential transistors (Q₁₅ , Q₁₆) for taking in data, a second pair of differential transistors (Q₁₃ , Q₁₄) for latching data taken into the first pair of differential transistors, a third pair of differential transistors (Q₄₃ , Q₄₄) for taking in scanning data, and a fourth pair of differential transistors (Q₄₁ , Q₄₂) for activating the second and third pair of differential transistors in a scanning mode, and a slave stage having a first pair of differential transistors (Q₂₅ , Q₂₆) for taking in data from the master stage, a second pair of differential transistors (Q₂₃ , Q₂₄) for latching data taken in to the first pair of differential transistors, a third pair of differential transistors Q₅₃ , Q₅₄) for latching scanning data, and a fourth pair of differential transistors (Q₅₁ , Q₅₂) for activating the first and third pair of differential transistors in the scanning mode.
Claim 2
Dependent Claim
193 words
A master-slave type flip-flop circuit including a normal function in a normal mode by a clock signal for flip-flop operation and a scanning function in a scanning mode by a scanning clock for testing an integrated circuit comprising: a master stage having a first pair of differential transistors (Q₁₅ , Q₁₆) for taking in data, a second pair of differential transistors (Q₁₃ , Q₁₄) for latching data taken into the first pair of differential transistors, a third pair of differential transistors (Q₄₃ , Q₄₄) for taking in scanning data, and a fourth pair of differential transistors (Q₄₁ , Q₄₂) for activating the second and third pair of differential transistors in a scanning mode, and a slave stage having a first pair of differential transistors (Q₂₅ , Q₂₆) for taking in data from the master stage, a second pair of differential transistors (Q₂₃ , Q₂₄) for latching data taken in to the first pair of differential transistors, a third pair of differential transistors Q₅₃ , Q₅₄) for latching scanning data, and a fourth pair of differential transistors (Q₅₁ , Q₅₂) for activating the first and third pair of differential transistors in the scanning mode.
Claim 3
Dependent Claim
39 words
A master-slave type flip-flop circuit as claimed in claim 1, wherein, in the master stage, said second pair of differential transistors (Q₁₃ , Q₁₄) is used in common to the normal mode and the scanning mode for latching data.
Claim 4
Dependent Claim
40 words
A master-slave type flip-flop circuit as claimed in claim 1, wherein, in the slave stage, said first pair of differential transistors (Q₂₅ , Q₂₆) is used in common to the normal mode and the scanning mode for taking in data.
Claim 5
Dependent Claim
34 words
A master-slave type flip-flop circuit as claimed in claim 1, wherein said clock signal is used for flip/flop operation and said scanning clock signal is held to a high level in the normal mode.
Claim 6
Dependent Claim
34 words
A master-slave type flip-flop circuit as claimed in claim 1, wherein said scanning clock is used for the scanning function and said clock signal is held to a high level in the scanning mode.