Patent EP0207313A2 successfully refreshed from Google Patents.
EP0207313A2
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Serial bus system
Assignee: HP Inc
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Filing: 1986-06-03
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Granted: —
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Expires: 2006-06-03
Abstract
Abstract A serial bus system in which frames are sent from a central station to a plurality of substations over a first conductor (TxD) and information is sent from the substation to the central station over a second conductor (RxD). Each transmitted frame contains bits identifying whether it is for address, data or a command. An addressed substation sends a handshake back to the central station by changing the logic level of the second conductor. An address frame contains a bit indicating whether a message is to be written into a register of a substation or read from a register therein. Any substation can interrupt to request service from the central station by changIng the logic level of the second conductor if the last command on the first conductor is an UNADDRESS command indicating the end of a message.
Inventors
- 👤 Genevieve M. Bliek
- 👤 Kent W. Luehman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
188 words
A serial bus system comprising a central station and a plurality of subsidiary stations, each of said stations having its own processor and each of said processors having an input and an output, characterized by a first conductor forming a single path between the output of the processor for said central station and the inputs of the processors for said subsidiary station, a second conductor forming a single path between the outputs of the processors for said substations and the input of the processor for said central station, the processor for said central station being programmed to form a frame including the bits contained in a selected register, and to place the bits of said frame onto said first conductor in series, the said frames having additional bits forming a transaction code identifying whether the frame is an address, data or a command, each of said processors for said subsidiary stations being programmed to respond to a frame on said first conductor that represents its address to momentarily change the logic level of said second conductor after the address frame, a subsequent data frame and certain command frames.
Claim 2
Dependent Claim
188 words
A serial bus system comprising a central station and a plurality of subsidiary stations, each of said stations having its own processor and each of said processors having an input and an output, characterized by a first conductor forming a single path between the output of the processor for said central station and the inputs of the processors for said subsidiary station, a second conductor forming a single path between the outputs of the processors for said substations and the input of the processor for said central station, the processor for said central station being programmed to form a frame including the bits contained in a selected register, and to place the bits of said frame onto said first conductor in series, the said frames having additional bits forming a transaction code identifying whether the frame is an address, data or a command, each of said processors for said subsidiary stations being programmed to respond to a frame on said first conductor that represents its address to momentarily change the logic level of said second conductor after the address frame, a subsequent data frame and certain command frames.
Claim 3
Dependent Claim
84 words
A serial bus system as set forth in claim 1 wherein the processor for said central station inserts a bit in a frame for an address indicating whether R/W data is to be sent to a substation or read from it, and wherein the processor for said substation is programmed to receive data if the bit has one logic level and to read from a register therein and place information so read onto said second conductor if the bit has the other logic level.
Claim 4
Dependent Claim
78 words
A serial bus system as set forth in claim 1 wherein the processor for said central station inserts a parity bit into each frame and wherein the processors for the substations are programmed to check the parity of a frame on the first conductor if that station is addressed and to place bits on said second conductor indicating whether or not the parity of a frame just received agrees with the parity bit inserted by the central station.
Claim 5
Dependent Claim
46 words
A serial bus system as set forth in claim 3 wherein the processor for the central station is programmed to retransmit a frame on said first conductor if the parity indicating bits are such that the parity of the frame received by the substation is incorrect.
Claim 6
Dependent Claim
55 words
A serial bus system as set forth in claim 1 wherein the processors for said substations are programmed to determine whether their stations are requesting service from the central station and for changing the logic level of said second conductor if such a request is present and if said first conductor is free for communication.
References Cited (Backward Citations)
No citation records indexed.
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