Patent EP0205809A2 successfully refreshed from Google Patents.
EP0205809A2
Expired / Lapsed
EP
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Vector processing
Assignee: International Business Machines Corp
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Filing: 1986-04-21
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Granted: —
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Expires: 2006-04-21
Abstract
Abstract A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.
Inventors
- 👤 Werner Buchholz
- 👤 Ronald Morton Smith
- 👤 David Siler Wehrly
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 12:43
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G06F9/30036; G06F9/30038; G06F9/3005; G06F9/30065; G06F9/32; G06F9/322; G06F9/325
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
177 words
In a data processing system including storage, registers including at least one vector register subdivided into vector element locations, operands including vector elements of at least one vector, means for loading and storing said operands in said storage and in said registers, and at least one central processing unit that executes instructions some of which operate on said operands, the method for operating on said vector elements comprising the. steps of: loading a first register with the number of said vector elements to be operated on by one of said instructions, updating at least one pointer register for continuously identifying the next vector element to be operated on by said one instruction, stopping the operation on each of said vector elements when said one instruction is interrupted, or when the last of said vector elements is operated on as indicated by said first register, and reissuing said one instruction after said one instruction is interrupted and resuming operation on one of said vector elements in at least one vector identified by said at least one pointer register.
Claim 2
Dependent Claim
177 words
In a data processing system including storage, registers including at least one vector register subdivided into vector element locations, operands including vector elements of at least one vector, means for loading and storing said operands in said storage and in said registers, and at least one central processing unit that executes instructions some of which operate on said operands, the method for operating on said vector elements comprising the. steps of: loading a first register with the number of said vector elements to be operated on by one of said instructions, updating at least one pointer register for continuously identifying the next vector element to be operated on by said one instruction, stopping the operation on each of said vector elements when said one instruction is interrupted, or when the last of said vector elements is operated on as indicated by said first register, and reissuing said one instruction after said one instruction is interrupted and resuming operation on one of said vector elements in at least one vector identified by said at least one pointer register.
Claim 3
Dependent Claim
65 words
The data processing system of Claim 1 in which said vector elements are stored in said at least one vector register and said at least one pointer register is an internal register that contains the number of the next vector element stored in said at least one vector register to be operated on in said at least one vector register by one of said instructions.
Claim 4
Dependent Claim
20 words
The data processing system of Claim 2 in which said at least one vector register is a vector mask register.
Claim 5
Dependent Claim
54 words
The data processing system of Claim 1 in which said vector elements are stored in said storage and said at least one pointer register is a general purpose register that contains the address of the next vector elements stored in said storage to be operated on in said storage by one of said instructions.
Claim 6
Dependent Claim
39 words
The data processing system of Claim 3 or 4 in which at least one of said instructions performs operations between said vector elements stored in said at least one vector register and said vector elements stored in said storage.
Claim 7
Dependent Claim
36 words
The data processing system of Claim 5 in which the number of said vector elements stored in said storage is greater than the number of said vector element locations in said at least one vector register.
Claim 8
Dependent Claim
44 words
The data processing system of Claim 6 in which said vector elements are operated on in sections of vector elements each section having a section size ranging from zero to the number of said vector element locations in said at least one vector register.
Claim 9
Dependent Claim
40 words
The data processing system of Claim 7 in which said first register is loaded with the smaller of the section size or the content of a third register which contains the number of said vector elements to be operated on.
Claim 10
Dependent Claim
33 words
The data processing system of Claim 8 in which the content of said first register is subtracted from the content of said third register with the result being loaded in said third register.
Claim 11
Dependent Claim
52 words
The data processing system of Claim 9 in which at least one of said instructions loads the smaller of said section size or said number of said vector elements to be operated on in said third register and subtracts the content of said first register from the content of said third register.
Claim 12
Dependent Claim
43 words
The data processing system of Claim 5 in which at least one of said instructions operating on said vector elements in said at least one vector register is completed when the content of said intemal register equals the content of said first register.
References Cited (Backward Citations)
No citation records indexed.
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