Patent EP0205801A1 successfully refreshed from Google Patents.
EP0205801A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interrupt mechanism for multi-microprocessing system having multiple busses
Assignee: International Business Machines Corp
•
Filing: 1986-04-18
•
Granted: —
•
Expires: 2006-04-18
Abstract
Abstract A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.
Inventors
- 👤 Sumit Dasgupta
- 👤 John Michael Hancock
- 👤 James Herbert Kukula
- 👤 Roger Edwin Peo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:00
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
156 words
In a multiprocessing system, the combination comprising: a global bus having a plurality of interrupt lines; an executive processor connected to said global bus and being operative to place interrupt requests on predetermined interrupt lines; and a plurality of cells connected to said global bus, each cell being connected to receive an interrupt request from a different one of said predetermined interrupt lines; each cell comprising a cell having a plurality of interrupt lines, and a plurality of cell processors each connected to a different one of said interrupt lines of said cell bus for receiving interrupt requests therefrom; the total number of cell processors exceeding the number of interrupt lines in said global bus, whereby each cell processor has a unique interrupt by virtue of each cell being connected to a different interrupt line in said global bus and each cell processor being connected to a different interrupt line in said cell bus connected thereto.
Claim 2
Dependent Claim
156 words
In a multiprocessing system, the combination comprising: a global bus having a plurality of interrupt lines; an executive processor connected to said global bus and being operative to place interrupt requests on predetermined interrupt lines; and a plurality of cells connected to said global bus, each cell being connected to receive an interrupt request from a different one of said predetermined interrupt lines; each cell comprising a cell having a plurality of interrupt lines, and a plurality of cell processors each connected to a different one of said interrupt lines of said cell bus for receiving interrupt requests therefrom; the total number of cell processors exceeding the number of interrupt lines in said global bus, whereby each cell processor has a unique interrupt by virtue of each cell being connected to a different interrupt line in said global bus and each cell processor being connected to a different interrupt line in said cell bus connected thereto.
Claim 3
Dependent Claim
47 words
The combination of Claim 1 wherein: in each of said cells, one cell processor is a master processor for receiving interrupt requests initiated by said executive processor, and each other cell processor in a cell is a slave processor for receiving interrupt requests from said master processor.
Claim 4
Dependent Claim
79 words
The combination of Claim 2 wherein said executive processor is operative to initiate an interrupt request for a given slave processor in one of said cells, such interrupt request being transmitted over said global bus by the one of said interrupt lines thereof associated with said one cell, to said master processor in such cell, said master processor in such cell being operative upon receipt of such interrupt request to transmit such interrupt request to said given slave processor.
Claim 5
Dependent Claim
63 words
The combination of Claim 1 comprising bus interface means interconnecting said global bus with each cell bus, said bus interface means comprising interrupt handling means for receiving an interrupt request from said global bus and interrupter means connected to said cell busses for placing such interrupt request on an interrupt line of such cell for interrupting a predetermined one of said cell processors.
Claim 6
Dependent Claim
60 words
The combination of Claim 4 wherein said bus interface means includes means responsive to the receipt of an interrupt request to send an acknowledgement to said executive processor and allow said executive processor to proceed with further processing while said interrupt request is being processed by said bus interface means and said cell to which the interrupt request is directed.
Claim 7
Dependent Claim
58 words
The combination of Claim 1 wherein said system comprises memory means distributed throughout said system, said memory means comprising a plurality of local memories each connected to a different one of said processors and a plurality of interface memories connected between each of said cell busses and said global bus and. associated with different ones of said cells.
Claim 8
Dependent Claim
87 words
The combination of Claim 6 wherein: said local memories connected to said cell processors each store interrupt handling routines, said executive processor being operative to transfer a message into the one of said interface memories associated with the given cell to which an interrupt request is directed, said message defining what work is to be done as a result of an interrupt request, and an interrupt handling routine in said local memory connected to said master processor in said given cell being operative to interpret said message.
Claim 9
Dependent Claim
30 words
The combination of Claim 7 including means in said system for processing interrupt vectors which point to which interrupt handling routine is to be used for handling an interrupt request.
References Cited (Backward Citations)
GB2059125A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.