Patent EP0205104A2 successfully refreshed from Google Patents.
EP0205104A2
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Intermediate potential generation circuit
Assignee: Toshiba Corp
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Filing: 1986-06-05
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Granted: —
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Expires: 2006-06-05
Abstract
Abstract @ Two intermediate potentials (Vn1, Vn2) of small current driving capacity are generated using load elements (R3, R4) and MOStransistors (Q1, Q2), and are respectively supplied to the gates of two MOS transistors (Q3, Q4) which are series-connected between power sources (Vcc, Vss) and have large current driving capacity, thus obtaining an intermediate potential (VR) from a node (N3) between the MOS transistors (Q3, Q4). The MOS transistors (Q3, Q4) atthe output stage are complementarily operated so as not to be turned on at the same time.
Inventors
- 👤 Yoshio C/O Patent Division Okada
- 👤 Mitsuru Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:01
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
283 words
An intermediate potential generation circuit formed in a semiconductor integrated circuit device, which produces an intermediate potential between power source voltages applied to said device, characterized by comprising: a first potential supply source (Vcc); a first load element (R3, Q5, Q7), one end of which is connected to said first potential supply source (Vcc); a first MOS transistor (Ql) of a first conductivity type, one end and a gate of which are connected to the other end of said first load element (R3, Q5, Q7); a second MOS transistor (Q2) of a second conductivity type, one end of which is connected to the other end of said first MOS transistor (Ql); a second load element (R4, Q6, Q8), one end of which is connected to the other end and a gate of said second MOS transistor (Q2); a second potential supply source (Vss) connected to the other end of said second load element (R4, Q6, Q8); a third MOS transistor (Q3) of the first conductivity type, which has one end connected to said first potential supply source (Vcc) and a gate connected to a node (Nl) between said first load element (R3, Q5, Q7) and said first MOS transistor (Ql); a fourth MOS transistor (Q4) which is connected between the other end of said third MOS transistor (Q3) and said second potential supply source (Vss), and which has a gate connected to a node (N2) between said second MOS transistor (Q2) and said second load element (R4, Q6, Q8): and an output terminal (11), connected to a node (N3) between said third and fourth MOS transistors (Q3, Q4), for outputting a potential (VR) between said first and second potential supply sources (Vcc, Vss).
Claim 2
Dependent Claim
283 words
An intermediate potential generation circuit formed in a semiconductor integrated circuit device, which produces an intermediate potential between power source voltages applied to said device, characterized by comprising: a first potential supply source (Vcc); a first load element (R3, Q5, Q7), one end of which is connected to said first potential supply source (Vcc); a first MOS transistor (Ql) of a first conductivity type, one end and a gate of which are connected to the other end of said first load element (R3, Q5, Q7); a second MOS transistor (Q2) of a second conductivity type, one end of which is connected to the other end of said first MOS transistor (Ql); a second load element (R4, Q6, Q8), one end of which is connected to the other end and a gate of said second MOS transistor (Q2); a second potential supply source (Vss) connected to the other end of said second load element (R4, Q6, Q8); a third MOS transistor (Q3) of the first conductivity type, which has one end connected to said first potential supply source (Vcc) and a gate connected to a node (Nl) between said first load element (R3, Q5, Q7) and said first MOS transistor (Ql); a fourth MOS transistor (Q4) which is connected between the other end of said third MOS transistor (Q3) and said second potential supply source (Vss), and which has a gate connected to a node (N2) between said second MOS transistor (Q2) and said second load element (R4, Q6, Q8): and an output terminal (11), connected to a node (N3) between said third and fourth MOS transistors (Q3, Q4), for outputting a potential (VR) between said first and second potential supply sources (Vcc, Vss).
Claim 3
Dependent Claim
52 words
A circuit according to claim 1, characterized in that a sum of absolute values of threshold voltages ( V tnl, Vtpl) of said first and second MOS transistors (Ql, Q2) is smaller than a sum of absolute values of threshold voltages (Vtn2, Vtp2) of said third and fourth MOS transistors (Q3, Q4).
Claim 4
Dependent Claim
62 words
A circuit according to claim 1, characterized in that a threshold voltage (Vtnl) of said first MOS transistor (Ql) is lower than a threshold voltage (Vtn2) of said third MOS transistor (Q3), and an absolute value of a threshold voltage (Vtpl) of said second MOS transistor (Q2) is smaller than that of a threshold voltage (Vtp2) of said fourth MOS transistor (Q4).
Claim 5
Dependent Claim
38 words
4 . A circuit according to claim 1, characterized in that a potential at a back gate of said second M OS transistor (Q2) is lower than that at a back gate of said fourth MOS transistor (Q4).
Claim 6
Dependent Claim
36 words
5 . A circuit according to claim 1, characterized in that a back gate of said second MOS transistor (Q2) is connected to a node between said first and second M O S transistors (Ql, Q2).
Claim 7
Dependent Claim
40 words
A circuit according to claim 1, characterized in that a back gate of said second MOS transistor (Q2) is connected to a node (Nl) between said first load element (R3, Q5, Q7) and said first MOS transistor ( Q l).
Claim 8
Dependent Claim
38 words
A circuit according to claim 1, characterized in that an impurity concentration of a channel region of said second MOS transistor (Q2) is higher than that of a channel region of said fourth MOS transistor ( Q4 ).
Claim 9
Dependent Claim
30 words
A circuit according to claim 1, characterized in that a channel length of said second MOS transistor ( Q 2) is smaller than that of said fourth MOS transistor (Q4).
Claim 10
Dependent Claim
33 words
A circuit according to claim 1, characterized in that channel widths of said third and fourth MOS transistors (Q3, Q4) are wider than those of said first and second MOS transistors (Ql, Q2).
Claim 11
Dependent Claim
31 words
A circuit according to claim 1, characterized in that said first and second load elements (R3, Q5, Q 7, R 4, Q6, Q8) respectively comprise resistors ( R 3, R4 ).
Claim 12
Dependent Claim
74 words
A circuit according to claim 1, characterized in that said first load element (R3, Q5, Q7) comprises an enhancement type MOS transistor (Q5) of the second conductivity type, a gate of which is connected to said second potential supply source (Vss), and said second load element (R4, Q6, Q8) comprises an enhancement type MOS transistor (Q6) of the first conductivity type, a gate of which is connected to said first potential supply source (Vcc).
Claim 13
Dependent Claim
74 words
A circuit according to claim 1, characterized in that said first load element (R3, Q5, Q7) comprises a depletion type MOS transistor (Q7) of the second conductivity type, a gate of which is connected to said first potential supply source (Vcc), and said second load element (R4, Q6, Q8) comprises a depletion type MOS transistor (Q8) of the first conductivity type, a gate of which is connected to said second potential supply source (Vss).
References Cited (Backward Citations)
No citation records indexed.
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