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EP0205010A2
Expired / Lapsed
EP
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Multiple port communications adapter apparatus
Assignee: International Business Machines Corp
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Filing: 1986-05-23
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Granted: —
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Expires: 2006-05-23
Abstract
Abstract A multi-port communications controller and variable protocol adapter is described. The adapter utilizes a user programmable pluggable programming cartridge for defining individual communications port data service characteristics. The port data service characteristics are interpreted by a microprocessor which manages the interchange from port to port and to or from memory or a host system. Direct memory access or interrupt driven memory access modes of operation are individually selectable for each individual in bound and out bound communications channel. The communications protocols employed at each port may be of any standard type with the microprocessor in the adapter making the appropriate conversion. Communication speeds can be automatically recognized and matched for each port also. An arbitration processor for both DMA and interrupt driven data transfer services is included as the heart of the communications adapter design to provide the capability of individualized control over each in bound and out bound channel's mode of data transfer service for the optimum mode of operation for each port and type of data service required.
Inventors
- 👤 Gilbert Stevens Burrus, Jr.
- 👤 Ronald Julius Cooper
- 👤 Michael Raymond Marr
- 👤 Mario Anthony Marsico
- 👤 John Carmine Pescatore
- 👤 Paul Douglas Sullivan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/32; G06F13/34
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
Apparatus to be used as a multi-port communications adapter, characterized in that it comprises : a processor having a data bus and an address bus connected thereto; control and arbitration means comprising a DMA and interrupt data transfer request arbitrator and controller DIAC means connected to said busses; at least one port interface communication means; an interrupt control logic means connected to said processor and to said DIAC and; a memory means connected to said busses; each said port interface communications means being connected to a communications link for transmitting or receiving signals thereon; each said port interface communication means having a means of presenting data transfer service request signals to said DIAC; said DIAC means being connected to receive said data transfer service request signals and being connected to said processor means via said busses for receiving data and addresses thereon; said DIAC means arbitrating among said data transfer service requests, identifying the requests by ports and selecting the highest presently requesting priority port's service request and, responsive thereto, presenting either an interrupt or DMA request to said processor in accordance with said data received from said processor, said data defining for each said port the said type of said request to be presented to said processor by said DIAC.
Claim 2
Dependent Claim
211 words
Apparatus to be used as a multi-port communications adapter, characterized in that it comprises : a processor having a data bus and an address bus connected thereto; control and arbitration means comprising a DMA and interrupt data transfer request arbitrator and controller DIAC means connected to said busses; at least one port interface communication means; an interrupt control logic means connected to said processor and to said DIAC and; a memory means connected to said busses; each said port interface communications means being connected to a communications link for transmitting or receiving signals thereon; each said port interface communication means having a means of presenting data transfer service request signals to said DIAC; said DIAC means being connected to receive said data transfer service request signals and being connected to said processor means via said busses for receiving data and addresses thereon; said DIAC means arbitrating among said data transfer service requests, identifying the requests by ports and selecting the highest presently requesting priority port's service request and, responsive thereto, presenting either an interrupt or DMA request to said processor in accordance with said data received from said processor, said data defining for each said port the said type of said request to be presented to said processor by said DIAC.
Claim 3
Dependent Claim
56 words
Apparatus according to claim 1 characterized in that : the interface communication means comprises an universal synchronous/asynchronous driver receiver port interface circuit USARTs, connected to the address and data busses for communicating data between said interface circuits USARTs, said processor and said memory in accordance with priority selections and interrupt or DMA controls from said DIAC.
Claim 4
Dependent Claim
84 words
Apparatus according to claim 1 or 2 to be used as a multi-port communication converter characterized in that: the microprocessor performs a communications protocol conversion; the memory means stores conversion instructions; the interface communication means accommodate logic level signals to communications device interface signal levels; the control and arbitration means presents the individual highest priority service request signal and appropriate memory location pointers to said processor to enable said processor for performing the chosen instructions for said selected highest priority port interface communication means.
Claim 5
Dependent Claim
61 words
Apparatus according to claims 1 and 2 to be used as a multi-port communications control system characterized in that : the processor provides initial control parameters to said control and arbitration means in accordance with said instructions in said memory for defining the mode of service to be accorded to each said interface communication means by said control and arbitration means.
Claim 6
Dependent Claim
71 words
Apparatus as described in Claims 1 through 4, characterized in that it comprises a line speed indication means comprising : a programmable timer connected to said data bus; and means in communication with said timer for reading the elapsed time between at least two successive said service requests from any one of said plurality of port interface; said elapsed time providing an indication of the communications line speed at said interface.
Claim 7
Dependent Claim
50 words
Apparatus as described in Claims 1 through 5, characterized in that : the control and arbitration means comprises a DMA mode processor and an interrupt mode processor and means for controlling which of said processors is applied to handling a said service request from each said port interface communication means.
References Cited (Backward Citations)
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