Apparatus for reducing test data storage requirements for high speed VLSI circuit testing

Claim 1

Apparatus, in an automatic testing system - (14,15), for supplying test data for a plurality of test cycles identifying test conditions for a multipin electronic circuit (11), comprising: a random access memory (17) having a plurality of addresses identifying memory rows containing test data for a plurality of test cycles; means for addressing said memory (17); and a hold register (16) for receiving each row of addressed data in said memory and supplying it to said testing system; characterized by: said random access memory (17) having a first plurality of higher order addresses identifying a plurality of memory rows each containing a complete field of test data, some of said rows further containing an operational code specifying a number of subsequent test cycles over which only a minority of data in said rows are to change without changing the remaining majority of data of the row, and having a smaller second number of lower order addresses identifying a second plurality of memory rows which contain test data in the same position within the data field as said minority of data; means (25) for sequentially addressing each of said higher order addresses; a repeat buffer (33) for sequentially addressing selected ones of said lower order addresses; and processor means (29-31, 37-41) for indexing said means (25) for sequentially addressing said higher order addresses and decoding each operational code received in said hold register (16), said processor connected to inhibit addressing by said means (25) for sequentially addressing said higher order addresses and to enable addressing by said repeat buffer (33) for a number of test cycles identified by said operational code whereby only said minority of data bits in said holding register - (16) having a field position corresponding to data bits in said lower order memory addresses change.

Claim 5

The apparatus of a preceding claim, further comprising: a source (40) of pulses corresponding to each test cycle; a counter (30) connected to receive a count indicating the number of consecutive test cycles specified by said operational code, said counter connected to inhibit said higher order address register (25) when a non-zero count is present and connected to be decremented in response to said test cycle pulses; said repeat buffer means (33) connected to be sequentially addressed by each of said test cycle pulses when said counter (30) indicates a non-zero count, said repeat buffer storing a series of selected lower order addresses of said random access memory (17) which contain consecutive test cycle data to be substituted for said minority of test data; said second address register (26) connected to address said lower order addresses in response to said repeat buffer output; and said processor means (29, 37) connected to decode said operational code produced when said random access memory contents are received in said hold register (16), and connected to provide a count to said counter (30) indicating the number of test cycles in which only said minority of test data are to be changed, whereby each succeeding pulse corresponding to a test cycle results in said repeat buffer (33) addressing said memory (17) replacing said minority of data in said hold register. (16) with data from said lower order addresses until said counter (30) decrements to zero.

Claim 6

A system for testing multipin LSSD integrated circuit structure, wherein data is produced for each test cycle defining a condition for each pin of an integrated circuit, containing an apparatus according to a preceding claim, for producing test data for each test cycle of said integrated circuit, characterized in that: said minority of data bits represent the test conditions for shift input and shift output terminals (SI, SO) of an LSSD structure.

Claim 8

The apparatus of a previous claim wherein said hold register (16) includes decoding circuitry which inhibits changing data in locations corresponding to said majority group of data bits in said second group of memory locations.