Configurable logic array

Claim 2

A shift register comprising: a plurality of dynamic storage cells 1 through K connected in series where K is a selected integer representing the maximum number of storage cells in series; means for transferring data sequentially from one cell to the next cell so as to fill all the cells of the shift register; and means for holding the data in each cell indefinitely.

Claim 3

structure as in Claim 1 including: means for generating from the data in said plurality of storage cells a corresponding plurality of configuration control bits to be used for controlling the configuration of a configurable logic element.

Claim 4

Structure as in Claim 1 wherein each of said storage cells comprises a first inverter possessing a first input lead and a first output lead, said first input lead having a first capacitance associated therewith; a second inverter possessing a second input lead and a second output lead, said second input lead having a second capacitance associated therewith; a first pass transistor connected between the output lead of said first inverter and the input lead of said second inverter; a second pass transistor connected between the output lead of said second inverter and the input lead of said first inverter, thereby to form a feedback path from said output lead of said second inverter to the input lead of the first inverter; means for turning on and off said first transistor; means for turning on and off said second transistor, wherein when said first and second pass transistors are turned on said first inverter and said second inverter are latched to maintain a given state.

Claim 5

Structure as in Claim 3 wherein said means for turning on and off said first transistor comprises a source of a clocking signal and said means for turning on and off said second transistor comprises a hold signal for latching up said first and said second inverter.

Claim 6

Structure as in Claim 4 including means for gating information in series from an external source into the first of said plurality of storage cells.

Claim 7

Structure as in Claim 1 wherein each cell holds a selected bit and its complement.

Claim 8

Structure as in Claim 3 wherein the data being transferred from one cell to the next is stored between transfer as a charge on said first capacitance and said second capacitance.

Claim 9

Structure comprising an integrated circuit comprising a plurality of logic elements, each of said logic elements composed of a number of semiconductor devices and being capable of being configured to perform any one of a plurality of logic functions; and means for configuring each of said logic elements to perform a selected one of said plurality of logic functions.

Claim 10

Structure comprising an integrated circuit comprising a plurality of logic elements, each of said logic elements composed of a number of semiconductor devices and being capable of being configured to perform any one of a plurality of logic functions; and means for configuring each of said logic elements to perform a selected one of said plurality of logic functions.

Claim 11

Structure as in Claim 8 wherein said semiconductor devices in each of said logic elements include a plurality of switches, said switches being capable of being activated by electrical signals to configure said semiconductor devices so as to perform a selected one of a set of logic functions.

Claim 12

Structure as in Claim 9 wherein said switches comprise pass transistors containing gates and said electrical signals comprise control signals to be applied to said gates.

Claim 13

Structure as in Claim 10 wherein each of said logic elements includes means for holding a plurality of control signals, said control signals controlling the states of the electronic switches in said logic element thereby to control the particular logic function carried out by said logic element.

Claim 14

Structure as in Claim 11 wherein each of said logic elements includes means for changing the control information contained in said logic element thereby to reconfigure the logic element to carry out another one of said set of functions.

Claim 15

Structure comprising a plurality of logic elements contained on a selected integrated circuit, each of said logic elements being interconnected by leads and switching elements thereby to form a configurable logic array.

Claim 16

Structure comprising a plurality of logic elements contained on a selected integrated circuit, each of said logic elements being interconnected by leads and switching elements thereby to form a configurable logic array.

Claim 17

Structure as in Claim 13 wherein said configurable logic array includes means for changing the state of each of the switches interconnecting said logic elements thereby to configure the configurable logic array to carry out any one of a plurality of logic functions.

Claim 20

Structure as in Claim 15 wherein said system is formed on a single monolithic integrated circuit.

Claim 21

Structure comprising a plurality of leads; and means for interconnecting any one of said plurality of leads to any other of said plurality of leads.

Claim 22

Structure comprising a plurality of leads; and means for interconnecting any one of said plurality of leads to any other of said plurality of leads.

Claim 23

Structure as in Claim 17 wherein said means for interconnecting any one of said plurality of leads to any other of said plurality of leads includes means for interconnecting any combination of said plurality of leads.

Claim 24

Structure as in Claim 18 wherein said means for interconnecting any combination of said plurality of leads comprises a multiplicity of pass transistors each of said pass transistors being arranged to interconnect one of said plurality of leads to another of said plurality of leads when said pass transistor is turned on.

Claim 25

Structure comprising N leads where N is a selected integer, each of said N leads not being connected to the others of said N leads; M pass transistors, where M is the number of pass transistors required to connect each one of said N leads to any one of the other of said N leads; and means for activating each of said M pass transistors thereby to form a conductive path from one of said N leads to another of said N leads.

Claim 26

Structure comprising N leads where N is a selected integer, each of said N leads not being connected to the others of said N leads; M pass transistors, where M is the number of pass transistors required to connect each one of said N leads to any one of the other of said N leads; and means for activating each of said M pass transistors thereby to form a conductive path from one of said N leads to another of said N leads.