EP0203384A2 — Multiple input circuit for field effect transisto…

Claim 1

Independent Claim 337 words

An integrated multiple input circuit (42) for applying a logic signal to the gate of a switching field effect transistor (FET) (88), characterized by: a) a first input branch (44) including a1 ) a first diode (52) having a first anode and a first cathode, a2) a first input node (P), a3) a first logic node (48 or 76) and a4) a first current source (58), wherein said first anode is electrically connected to said first input node (P), said first cathode is electrically connected to said first logic node (48 or 76) and said first current source (58) is electrically connected to said first logic node (48 or 76); b) a second input branch (46) including b1) a second diode (60) having a second anode and a second cathode, b2) a second input node (X), b3) a second logic node (50 or 78) and b4) a second current source (66), wherein said second anode is electrically connected to said second input node (X), said second cathode is electrically connected to said second logic node (50 or 78) and said second current source (66) is electrically connected to said second logic node (50 or 78); c) a third logic node (80); d) a third diode (82) having a third cathode and a third anode, wherein said third anode is electrically connected to said third logic node (80) and said third cathode is electrically connected to said first logic node (48 or 76); e) a fourth diode (84) having a fourth cathode and a fourth anode, wherein said fourth anode is electrically connected to said third logic node (80) and said fourth cathode is electrically connected to said second logic node - (50 or 78); f) a third current source (86) electrically connected to said third logic node (80); and wherein said third logic node (80) is electrically connected to said gate (in 88) so that said third logic node (80) provides a logic function for logic data input at said first (P) and second (X) logic nodes.

Claim 2

Dependent Claim 337 words

An integrated multiple input circuit (42) for applying a logic signal to the gate of a switching field effect transistor (FET) (88), characterized by: a) a first input branch (44) including a1 ) a first diode (52) having a first anode and a first cathode, a2) a first input node (P), a3) a first logic node (48 or 76) and a4) a first current source (58), wherein said first anode is electrically connected to said first input node (P), said first cathode is electrically connected to said first logic node (48 or 76) and said first current source (58) is electrically connected to said first logic node (48 or 76); b) a second input branch (46) including b1) a second diode (60) having a second anode and a second cathode, b2) a second input node (X), b3) a second logic node (50 or 78) and b4) a second current source (66), wherein said second anode is electrically connected to said second input node (X), said second cathode is electrically connected to said second logic node (50 or 78) and said second current source (66) is electrically connected to said second logic node (50 or 78); c) a third logic node (80); d) a third diode (82) having a third cathode and a third anode, wherein said third anode is electrically connected to said third logic node (80) and said third cathode is electrically connected to said first logic node (48 or 76); e) a fourth diode (84) having a fourth cathode and a fourth anode, wherein said fourth anode is electrically connected to said third logic node (80) and said fourth cathode is electrically connected to said second logic node - (50 or 78); f) a third current source (86) electrically connected to said third logic node (80); and wherein said third logic node (80) is electrically connected to said gate (in 88) so that said third logic node (80) provides a logic function for logic data input at said first (P) and second (X) logic nodes.

Claim 3

Dependent Claim 17 words

The circuit of claim 1, characterized in that the third logic node (80) provides and AND function.

Claim 4

Dependent Claim 200 words

The circuit of claim 1, characterized in that said first input branch (44) further includes a first plurality of diodes (e.g. 54) and a first plurality of input nodes (e.g. Q), wherein the anode of each of said first plurality of diodes (e.g. 54) is connected to one of said first plurality of input nodes (e.g. Q) and the cathode of each of said first plurality of diodes is electrically connected to said first logic node (48 or 76); and said second input branch (46) further includes a second plurality of diodes (e.g. 62) and a second plurality of input nodes (e.g. Y), wherein the anode of each of said second plurality of diodes (e.g. 62) is connected to one of said second plurality of input nodes - (Y) and the cathode of each of said second plurality of diodes (62) is electrically connected to said second logic node (50 or 78), so that said first logic node (48 or 76) provides a logic OR function for data signals input to said first plurality of inputs and said second logic node (50 or 78) provides a logical OR function for data signals input to said second plurality of input nodes.

Claim 5

Dependent Claim 142 words

The circuit of claim 1, 2 or 3, characterized by g) a third input node (Q); h) a fifth diode (54) having a fifth anode and fifth cathode, wherein said fifth anode is electrically connected to said third input node and said fifth cathode is electrically connected to said first logic nodes; i) a fourth input node (Y); and j)a sixth diode (62) having a sixth anode and a sixth cathode, wherein said sixth anode is electrically connected to said fourth input node and said sixth cathode is electrically connected to said second logic node, so that said first logic node provides a logic OR function for data signals applied to said first (P) and third input nodes (Q), and said second logic node provides a logic OR function for data signals applied to said second (X) and fourth (Y) input nodes.

Claim 6

Dependent Claim 57 words

The circuit of claim 4, characterized by k) first voltage level shifting means (68 & 70) electrically connected between said first logic node (e.g. 48) and said first current source (58); and I) second voltage level shifting means (72 & 74) electrically connected between said second logic node (e.g 50) and said second current source - (66).

Claim 7

Dependent Claim 74 words

The circuit of claim 5, characterized in that said first voltage level shifting means (68 & 70) includes at least one voltage level shifting diode (68) adapted to pass substantial current only in the same direction as said first diode (52);`and said second voltage level shifting means (72 & 74) includes at least one voltage level shifting diode (72) adapted to pass substantial current only in the same direction as said second diode (60).

Claim 8

Dependent Claim 16 words

The circuit of one of the preceding claims, characterized in that all diodes are Schottky diodes.

Claim 9

Dependent Claim 62 words

The circuit of one of the preceding claims, characterized in that said first (58), second - (66) and third (86) current sources are each field effect transistors (FET), wherein each of said current source FETs has a gate and a source, and said gate of each current source FET is directly electrically connected to said source of the same current source FET.

Claim 10

Dependent Claim 100 words

The circuit of claim 8, characterized in that switching FET (88) also has a drain and a source, and further including a fourth current source (90) electrically connected to the drain of said switching FET; and an output node (92), said output node being electrically connected to the drain of said FET; wherein said fourth current source is electrically connected to a voltage supply (V DD ) and the source of said switching FET is electrically connected to a voltage reference point (ground), so that the logic condition at said third logic node can be inverted at said output node.

Claim 11

Dependent Claim 16 words

The circuit of claim 9, characterized in that said switching FET is an enhancement mode device.

Claim 12

Dependent Claim 15 words

The circuit of claim 9, characterized in that switching FET is an enhancement mode device.

Claim 13

Dependent Claim 309 words

A multiple integrated input OR/AND logic circuit (42) for applying a logic signal to the gate of a switching field effect transistor (FET) (88), characterized by: m) a first circuit branch (44) for providing an OR logic function, said first circuit branch including a first logic node (48 or 76), a first plurality of input nodes (P & Q) and a first plurality of diodes (e.g. 54) with the anode of one and only one of said first plurality of diodes being directly electrically - connected to one and only one of said first plurality of input nodes, and the cathodes of said first plurality of diodes being electrically connected in common at said first logic node; n) a second circuit branch (46) for providing an OR logic function, said second circuit branch including a second logic node (50 or 78), a second plurality of input nodes (X & Y) and a second plurality of diodes (e.g. 62) with the anode of one and only one of said second plurality of diodes being directly electrically connected to one and only one of said second plurality of input nodes, and the cathodes of said second plutality of diodes being directly electrically connected in common at said second logic node; o) an AND circuit portion for providing an AND logic function for the logic conditions at said first and second logic nodes, said AND portion including a third logic node (80), and first (82) and second (82) AND diodes, with the anodes of said first and second AND diodes being directly electrically" connected in common at said third logic node, the cathode of said first AND diode being etectrically connected to said first logic node, the cathode of said second AND diode being electrically connected to said second logic node and said third logic node being electrically connected to said gate.

Claim 14

Dependent Claim 309 words

A multiple integrated input OR/AND logic circuit (42) for applying a logic signal to the gate of a switching field effect transistor (FET) (88), characterized by: m) a first circuit branch (44) for providing an OR logic function, said first circuit branch including a first logic node (48 or 76), a first plurality of input nodes (P & Q) and a first plurality of diodes (e.g. 54) with the anode of one and only one of said first plurality of diodes being directly electrically - connected to one and only one of said first plurality of input nodes, and the cathodes of said first plurality of diodes being electrically connected in common at said first logic node; n) a second circuit branch (46) for providing an OR logic function, said second circuit branch including a second logic node (50 or 78), a second plurality of input nodes (X & Y) and a second plurality of diodes (e.g. 62) with the anode of one and only one of said second plurality of diodes being directly electrically connected to one and only one of said second plurality of input nodes, and the cathodes of said second plutality of diodes being directly electrically connected in common at said second logic node; o) an AND circuit portion for providing an AND logic function for the logic conditions at said first and second logic nodes, said AND portion including a third logic node (80), and first (82) and second (82) AND diodes, with the anodes of said first and second AND diodes being directly electrically" connected in common at said third logic node, the cathode of said first AND diode being etectrically connected to said first logic node, the cathode of said second AND diode being electrically connected to said second logic node and said third logic node being electrically connected to said gate.

Claim 15

Dependent Claim 30 words

The circuit of one-of the preceding claims, characterized in that said circuit is integrated in a gallium arsenide (GaAs) substrate and said switching FET (88) is a metal-semiconductor FET (MESFET).

Claim 16

Dependent Claim 20 words

The circuit of one of the preceding claims, characterized in that said switching FET (88) is a metal-oxide-semiconductor FET (MOSFET).

Claim 17

Dependent Claim 22 words

The circuit of one of the claims 1 to 13, characterized in that said switching FET (88) is a metal-insulator-semiconductor FET (MISFET).

Claim 18

Dependent Claim 21 words

The circuit of one of the claims 1 to 13, characterized in that said-switching FET (88) is a junction FET (JFET).

Claim 19

Dependent Claim 23 words

The circuit of one of the claims ' 1 to 13, characterized in that said switching FET (88) is a modulation-doped FET (MODFET).

Multiple input circuit for field effect transistors

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag