EP0202675A2 — Input/output control system

Claim 1

Independent Claim 199 words

An input/output control system (IOC), the 10C system being operatively connected, via a common bus (C-BUS), with a central control unit (CC) and being operatively connected, via an external bus - (E-BUS), with an input/output unit (10), so as to control a transfer of data to be communicated between the central control unit (CC) and the input/output unit (10) characterized in that the following three units are further introduced to the IOC system: a buffer memory in which transfer data is momentarily stored; a control register (REG) in which a plurality of sets of data transfer control information, given from the central control unit (CC), are written, and; a direct memory access control means being operative, under a command from a microprocessor - (uP) with the use of data transfer control information written in said control register (REG), to achieve a data transfer control with respect to said buffer memory, where a data transfer is performed by accessing the input/output unit (10) via an input/output unit control circuit (IOCTL) for controlling the unit (10), and both processes for starting and finishing operations of the control circuit (IOCTL) are carried out by the microprocessor (u.P) which executes a predetermined microprogram.

Claim 2

Dependent Claim 199 words

An input/output control system (IOC), the 10C system being operatively connected, via a common bus (C-BUS), with a central control unit (CC) and being operatively connected, via an external bus - (E-BUS), with an input/output unit (10), so as to control a transfer of data to be communicated between the central control unit (CC) and the input/output unit (10) characterized in that the following three units are further introduced to the IOC system: a buffer memory in which transfer data is momentarily stored; a control register (REG) in which a plurality of sets of data transfer control information, given from the central control unit (CC), are written, and; a direct memory access control means being operative, under a command from a microprocessor - (uP) with the use of data transfer control information written in said control register (REG), to achieve a data transfer control with respect to said buffer memory, where a data transfer is performed by accessing the input/output unit (10) via an input/output unit control circuit (IOCTL) for controlling the unit (10), and both processes for starting and finishing operations of the control circuit (IOCTL) are carried out by the microprocessor (u.P) which executes a predetermined microprogram.

Claim 3

Dependent Claim 91 words

A system as set forth in claim 1, wherein said direct memory access control means is comprised of an input/output unit direct memory access control circuit (IDMACTL) and a direct memory access control circuit (DMACTL), in which the control circuit (IDMACTL) is operative to perform the data transfer between said buffer memory and the input/output unit control circuit (IOCTL), while the control circuit (IDMACTL) is operative to perform the data transfer between the buffer memory and a common bus (C-BUS) located between the IOC system and the central control unit (CC).

Claim 4

Independent Claim 94 words

A system as set forth in c)aim 2, wherein a program mode control circuit (PMCTL) is connected with the common bus (C-BUS) to achieve the transfer control under a program mode (PM), and the microprocessor (µP) is directly activated, via the control circuit (PMCTL), by an interruption for activation which occurs when a data transfer request is issued from the central control circuit - (CC) and, when the related data transfer comes to an end, said activation is released by an interruption for finish which is issued from the input/output unit control circuit (IOCTL).

Claim 5

Independent Claim 94 words

A system as set forth in c)aim 2, wherein a program mode control circuit (PMCTL) is connected with the common bus (C-BUS) to achieve the transfer control under a program mode (PM), and the microprocessor (µP) is directly activated, via the control circuit (PMCTL), by an interruption for activation which occurs when a data transfer request is issued from the central control circuit - (CC) and, when the related data transfer comes to an end, said activation is released by an interruption for finish which is issued from the input/output unit control circuit (IOCTL).

Claim 6

Dependent Claim 19 words

A system as set forth in claim 3, wherein said buffer memory is made of a first-in/first-out memory (FIFO).

Claim 7

Dependent Claim 129 words

A system as set forth in claim 4, wherein the first-in/first-out memory (FIFO) is provided with an input terminal(D in ) for a write data, an output terminal (D out ) for a read data, a write mode command reception terminal (W), a read mode command reception terminal (R), a terminal (FUL) for an indication of a full status "FULL" of the memory (FIFO) with the transfer data, and a terminal (EMP) for a indication of an empty status "EMPTY" of the memory (FIFO), also the input/output unit control circuit (IOCTL) is provided with a write mode command reception terminal (W) for starting the input/output unit (10) under the write mode, and a read mode command reception terminal (R) for starting the input/output unit (10) under the read mode.

Claim 8

Dependent Claim 109 words

A system as set forth in claim 5, wherein the input/output unit direct memory access control circuit (IDMACTL) is operative to receive an output from a first logic gate, as an control input, to produce, first, a signal to be applied to the terminal (W) or the terminal (R), both provided by the first-in/first-out memory (FIFO), and, second, a signal to be applied to the terminal (W) or the terminal (R), both provided by the input/output unit control circuit (IOCTL), and said first logic gate is supplied with, as its input, at least, each output from the terminal (FUL) and the terminal (EMP), both provided by the memory (FIFO).

Claim 9

Dependent Claim 119 words

A system as set forth in claim 6, wherein the direct memory access mode control circuit - (DMACTL) produces a signal to be applied to the terminal (W) or the terminal (R), both provided by . the first-in/first-out memory (FIFO), by receiving, as its control input, the output from a second logic gate which is supplied with, as its input, at least, each output from the terminal (FUL) and the terminal (EMP), both provided by the memory (FIFO), . and an information indicative of "WCR = 0", that is the number of the transfer words reaches zero, which number is specified by corresponding one of the sets of said data transfer control information written in the control register (REG).

Claim 10

Dependent Claim 66 words

A system as set forth in claim 7, wherein the first-in/first-out memory (FIFO) is commonly used for the one way data transfer and the other way data transfer, selectively, the former transfer is performed from the common bus (C-BUS) to the input/output unit (10), i.e., the write mode, while the latter transfer is performed from the unit (10) to the bus (C-BUS), i.e., the read mode.

Claim 11

Dependent Claim 83 words

A system as set forth in claim 8, wherein said first logic gate and second logic gate are supplied commonly with a transfer direction specifying information (DIR), so that both the input/output unit direct memory access mode control circuit - (IDMACTL) and the direct memory access mode control circuit (DMACTL) are specified to operate under the write mode or the read mode, selectively, which information (DIR) is one of said sets of said data transfer control information written in the control register (REG).

Claim 12

Dependent Claim 89 words

A system as set forth in claim 9, wherein said second logic gate is further supplied with an input given from a time supervisor (TIMSV) which is operative to detect a common bus (C-BUS) time out, the common bus (C-BUS) time out representing a condition that no response is returned, after an elapse of a predetermined term, from the central control, which response is to be generated for a control signal (S CTL ) sent, from the direct memory access mode control circuit (DMACTL), on the common bus (C-BUS).

Claim 13

Independent Claim 48 words

A system as set forth in claim , wherein said second logic gate is further supplied with an input given from a parity check part (PTYCHK) which is operative to detect a parity error contained, if any, in said transfer data provided on the common bus - (C-BUS).

Claim 14

Dependent Claim 77 words

A system as set forth in claim 8, wherein the first-in/first-out memory (FIFO) cooperates with a selector (SEL), located at the front stage of the input terminal (W) provided by the memory (FIFO), the selector (SEL) is switched by the control of the direct memory access mode control circuit - (DMACTL), so that the transfer data from the common bus (C-BUS) and the transfer data from the input/output unit (10) are selectively stored in the memory (FIFO).

Claim 15

Dependent Claim 98 words

A system as set forth in claim 9, wherein the direct memory access mode control circuit - (DMACTL) is operative to increment by + 1 a main memory address information for a main memory - (MM), connected to the common bus C-BUS, every time each transfer data is supplied, via the common bus (C-BUS), to the main memory (MM), which main memory address information is one of said sets of said data transfer control information written in the control register (REG) to specify the address of the main memory at which each transfer data is to be written.

Claim 16

Dependent Claim 42 words

A system as set forth in claim 5, wherein a diagnostic check part (DIGC) is further incorporated in the system for executing a diagnostic operation with regard to the first-in/first-out memory (FIFO), the input/output unit (10) and the microprocessor - (µP), selectively.

Claim 17

Dependent Claim 43 words

A system as set forth in claim 14, wherein the diagnostic check part is operative to momentarily stop issuance of said data transfer request to the input/output unit direct access mode control circuit (IDMACTL) and/or the direct memory access mode circuit (DMACTL), selectively.

Claim 18

Dependent Claim 35 words

The system as set forth in claim 15, wherein the diagnostic check part (DIGC) is further operative to issue a command for write or read to the first-in/first-out memory (FIFO) under control of said microprogram.

Claim 19

Dependent Claim 115 words

The system as set forth in claim 16, wherein the diagnostic check part (DIGC) sets up, at least, a first diagnostic mode, a second diagnostic mode and a third diagnostic mode, selectively, in which, under the first diagnostic mode, a related diagnostic check data (DD) is communicated only between the microprocessor (µP) and the first-in/first-out memory (FIFO), under the second mode, a related diagnostic check data (DD) is communicated only by way of the microprocessor (aP), the memory - (FIFO) and the input/output unit (10), and under the third mode, a related diagnostic check data (DD) is communicated only by way of the microprocessor - (aP), the memory (FIFO) and the central control unit (CC).

Claim 20

Dependent Claim 157 words

A system as set forth in claim 17, wherein the diagnostic check portion (DIGC) is comprised of logic gates (G20 through G23) at least, the logic gates (G20 through G23) are supplied with at least four sets of information, first, a transfer direction specifying information (DIR) generated by said microprogram, second, an information (IDMAEX) indicative of command for exciting the input/output unit direct memory access mode control circuit - (IDMACTL), third, an information (DMAEX) indicative of command for exciting the direct memory access mode control circuit (DMACTL), and fourth, either said "FULL" status information or said "EMPTY" status information regarding the first-in/first-out memory (FIFO), and thus, a read request (RREQ1) given to the control circuit (IDMCTL), a read request (RREQ2) given to the control circuit - (DMACTL), a write request (WREQ1) given to the control circuit (IDMCTL) and a write request (WREQ2) given to the control circuit (DMACTL) are output from respective logic gates G20 through G23.

Claim 21

Dependent Claim 48 words

A system as set forth in claim 18, wherein the diagnostic check portion (DIGC) is operative to detect that no problem has occurred in the first-in/first-out memory (FIFO), in the input/output unit - (10) and in the microprocessor (µP), respectively under said first, second and third diagnostic modes.

Claim 22

Dependent Claim 67 words

A system as set forth in claim 17, wherein the diagnostic check portion (DIGC) is also operative to set up a fifth mode in which the transfer data in the first-in/first-out memory (FIFO) is processed to form another transfer data with the aid of the microprocessor (µP) and then rewritten in the memory (FIFO), so that the thus processed data is stored in the input/output unit (10).

Claim 23

Dependent Claim 24 words

A system as set forth in claim 20, wherein the microprocessor (µP) executes a process for a cipher with respect to said transfer data.

Input/output control system

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