Abstract An optical pulse receiving circuit comprises a photoelectric conversion circuit and a comparison circuit, of which one of two input terminals is connected to the output of said photoelectric conversion circuit, while a voltage with a value obtained by reducing the maximum value of output pulse voltage of said photoelectric conversion circuit by a predeter-. mined proportion is applied to the other input terminal of said comparison circuit, which provides either high or low output voltage according to the magnitude of both input voltages. Also a predetermined number of bias voltages can be applied to said other input terminal.
An optical pulse receiving circuit comprising a photoelectric conversion circuit and a comparison circuit and wherein an output of said photoelectric conversion circuit is coupled to one of two input terminals of said comparison circuit, while a voltage with a value obtained by reducing the maximum value of output pulse voltage of said photoelectric conversion circuit by a predetermined proportion is applied to the other input terminal of said comparison circuit, said comparison circuit being adapted to provide either high or low output voltage according to the magnitude of said both input voltages.
Claim 2
Dependent Claim
93 words
An optical pulse receiving circuit comprising a photoelectric conversion circuit and a comparison circuit and wherein an output of said photoelectric conversion circuit is coupled to one of two input terminals of said comparison circuit, while a voltage with a value obtained by reducing the maximum value of output pulse voltage of said photoelectric conversion circuit by a predetermined proportion is applied to the other input terminal of said comparison circuit, said comparison circuit being adapted to provide either high or low output voltage according to the magnitude of said both input voltages.
Claim 3
Dependent Claim
37 words
An optical pulse receiving circuit in accordance with claim 1 wherein a predetermined number of bias voltages are applied to said input terminal of said comparison circuit to which is applied said voltage obtained by said reduction.
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