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EP0202477A2
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EP
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Method of forming an electrical short circuit between adjoining regions in an insulated gate semiconductor device
Assignee: General Electric Co
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Filing: 1986-04-17
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Granted: —
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Expires: 2006-04-17
Abstract
Abstract A method of forming an electrical short circuit between adjoining regions of an insulated gate semiconductor device uses retained portions of insulating layers formed over gate electrodes as an etching mask. The insulating layers are formed over the exposed surfaces of the insulated gate device, including the gate electrodes, and are then selectively removed to leave the retained portions covering the gate electrode top surfaces and sidewalls while exposing selected areas of a semiconductor substrate. The retained portions of the insulating layers are then used as an etching mask to etch away selected portions of the adjoining regions in the semiconductor substrate and expose a junction therebetween. The electrical short circuit is subsequently formed at the exposed junction.
Inventors
- 👤 Tat-Sing Paul Chow
- 👤 Bantval Jayant Baliga
- 👤 Robert Paul Love
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:03
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/035; H10D12/411; H10D12/441; H10D12/461; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P50/69; H10P50/691; H10P50/693; H10P50/695
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
329 words
A method of forming an electrical short circuit between adjoining regions of a semiconductor device; said semiconductor device comprising, in a semiconductor substrate having a major surface, a first region of a first conductivity type and a second region of a second conductivity type adjoining said first region and forming a junction therewith; said second region including a top surface comprising a portion of said major surface of said semiconductor substrate; said semiconductor device further comprising at least two electrically connected electrodes, each of said electrodes being spaced from said major surface of said semiconductor substrate; each of said electrodes having a top surface and a sidewall, the sidewalls of the respective electrodes being in opposed, laterally spaced relation; each of said electrodes overlying a respective, different portion of said top surface of said second region whereby each of said sidewalls of said electrodes overlies said top surface of said second region; said method comprising the steps of: forming respective portions of a first insulating layer over said top surfaces of said electrodes, each of said first insulating layer portions including a sidewall substantially in registry with the sidewall of its respective underlying electrode, and a top surface; forming a conformal second insulating layer over the portion of said semiconductor device between said sidewalls of said electrodes, over said sidewalls of said electrodes and over said sidewalls and top surfaces of said first insulating layer portions; selectively removing part of said second insulating layer to leave retained portions thereof covering said sidewalls of said electrodes and said sidewalls of said first insulating layer portions; selectively etching said semiconductor device utilizing said first insulating layer portions and said retained portions of said second insulating layer as etching masks to remove parts of said first and second regions and expose an edge of said junction; and forming an electrically conductive layer at said exposed edge of said junction to form thereat an electrical short circuit between said first and second regions.
Claim 2
Independent Claim
329 words
A method of forming an electrical short circuit between adjoining regions of a semiconductor device; said semiconductor device comprising, in a semiconductor substrate having a major surface, a first region of a first conductivity type and a second region of a second conductivity type adjoining said first region and forming a junction therewith; said second region including a top surface comprising a portion of said major surface of said semiconductor substrate; said semiconductor device further comprising at least two electrically connected electrodes, each of said electrodes being spaced from said major surface of said semiconductor substrate; each of said electrodes having a top surface and a sidewall, the sidewalls of the respective electrodes being in opposed, laterally spaced relation; each of said electrodes overlying a respective, different portion of said top surface of said second region whereby each of said sidewalls of said electrodes overlies said top surface of said second region; said method comprising the steps of: forming respective portions of a first insulating layer over said top surfaces of said electrodes, each of said first insulating layer portions including a sidewall substantially in registry with the sidewall of its respective underlying electrode, and a top surface; forming a conformal second insulating layer over the portion of said semiconductor device between said sidewalls of said electrodes, over said sidewalls of said electrodes and over said sidewalls and top surfaces of said first insulating layer portions; selectively removing part of said second insulating layer to leave retained portions thereof covering said sidewalls of said electrodes and said sidewalls of said first insulating layer portions; selectively etching said semiconductor device utilizing said first insulating layer portions and said retained portions of said second insulating layer as etching masks to remove parts of said first and second regions and expose an edge of said junction; and forming an electrically conductive layer at said exposed edge of said junction to form thereat an electrical short circuit between said first and second regions.
Claim 3
Dependent Claim
46 words
The method of Claim 1 wherein said semiconductor substrate comprises silicon and the step of forming said electrically conductive layer comprises forming a layer of metal on said silicon and annealing said device at a temperature at which said metal forms a silicide with said silicon.
Claim 4
Dependent Claim
25 words
The method of Claim 1 wherein the step of forming said electrically conductive layer comprises forming said layer by selective chemical vapor deposition of metal.
Claim 5
Dependent Claim
21 words
The method of Claim 1 wherein said second insulating layer is selectively removed by the application thereto of a directional etchant.
Claim 6
Dependent Claim
22 words
The method of Claim 4 wherein said directional etchant comprises a radio frequency plasma of tetrafluoromethane and hydrogen or trifluoromethane and helium.
Claim 7
Dependent Claim
81 words
The method of Claim 4 wherein: said junction has a generally U-shaped, cross-sectional configuration including a pair of legs each terminating in a respective end at said major surface of said semiconductor substrate; said top surface of said second region is bounded on two sides by said respective ends of said pair of junction legs; and each of said electrodes overlies a respective one of said junction legs whereby said exposed junction edge is created intermediate said pair of junction legs.
Claim 8
Dependent Claim
38 words
The method of Claim 6 wherein: each of said first and second regions comprises silicon semiconductor material; said first insulating layer comprises silicon nitride or silicon dioxide; and said second insulating layer comprises silicon nitride or silicon dioxide.
Claim 9
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 1.
Claim 10
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 6.
Claim 11
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 7.
Claim 12
Independent Claim
404 words
A method of forming an electrical short circuit between adjoining regions of a semiconductor device; said semiconductor device comprising, in a semiconductor substrate having a major surface, a drift region of a first conductivity type, a base region of a second conductivity type adjoining said drift region, and an emitter region of said first conductivity type adjoining said base region and forming an emitter-base junction therewith; said emitter-base junction having a generally U-shaped, cross-sectional configuration including a pair of legs each terminating in a respective end at said major surface of said semiconductor substrate; said emitter region including a top surface comprising a portion of said major surface of said semiconductor substrate bounded on two sides by said respective ends of said pair of emitter-base junction legs; said semiconductor device further comprising at least two electrically connected gate electrodes, each of said gate electrodes being spaced from said major surface of said semiconductor substrate; each of said gate electrodes having a top surface and a sidewall, the sidewalls of the respective gate electrodes being in opposed, laterally spaced relation; each of said gate electrodes overlying a respective single leg of said pair of emitter-base junction legs, whereby each of said sidewalls of said gate electrodes overlies said top surface of said emitter region; said method comprising the steps of: forming respective portions of a first insulating layer over said top surfaces of said gate electrodes, each of raid first insulating layer portions including a sidewall substantially in registry with the sidewall of its respective underlying gate electrode, and a top surface; forming a conformal second insulating layer over the portion of said semiconductor device between said sidewalls of said gate electrodes, over said sidewalls of said gate electrodes and over said sidewalls and top surfaces of said first insulating layer portions; selectively removing part of said second insulating layer to leave retained portions thereof covering said sidewalls of said gate electrodes and said sidewalls of said first insulating layer portions; selectively etching said semiconductor device utilizing said first insulating layer portions and said retained portions of said second insulating layer as etching masks to remove parts of said emitter and base regions and expose an edge of said emitter-base junction intermediate said pair of legs thereof; and forming a first electrically conductive layer at said exposed edge of said emitter-base junction to form thereat an electrical short circuit between said emitter and base regions.
Claim 13
Independent Claim
404 words
A method of forming an electrical short circuit between adjoining regions of a semiconductor device; said semiconductor device comprising, in a semiconductor substrate having a major surface, a drift region of a first conductivity type, a base region of a second conductivity type adjoining said drift region, and an emitter region of said first conductivity type adjoining said base region and forming an emitter-base junction therewith; said emitter-base junction having a generally U-shaped, cross-sectional configuration including a pair of legs each terminating in a respective end at said major surface of said semiconductor substrate; said emitter region including a top surface comprising a portion of said major surface of said semiconductor substrate bounded on two sides by said respective ends of said pair of emitter-base junction legs; said semiconductor device further comprising at least two electrically connected gate electrodes, each of said gate electrodes being spaced from said major surface of said semiconductor substrate; each of said gate electrodes having a top surface and a sidewall, the sidewalls of the respective gate electrodes being in opposed, laterally spaced relation; each of said gate electrodes overlying a respective single leg of said pair of emitter-base junction legs, whereby each of said sidewalls of said gate electrodes overlies said top surface of said emitter region; said method comprising the steps of: forming respective portions of a first insulating layer over said top surfaces of said gate electrodes, each of raid first insulating layer portions including a sidewall substantially in registry with the sidewall of its respective underlying gate electrode, and a top surface; forming a conformal second insulating layer over the portion of said semiconductor device between said sidewalls of said gate electrodes, over said sidewalls of said gate electrodes and over said sidewalls and top surfaces of said first insulating layer portions; selectively removing part of said second insulating layer to leave retained portions thereof covering said sidewalls of said gate electrodes and said sidewalls of said first insulating layer portions; selectively etching said semiconductor device utilizing said first insulating layer portions and said retained portions of said second insulating layer as etching masks to remove parts of said emitter and base regions and expose an edge of said emitter-base junction intermediate said pair of legs thereof; and forming a first electrically conductive layer at said exposed edge of said emitter-base junction to form thereat an electrical short circuit between said emitter and base regions.
Claim 14
Dependent Claim
47 words
The method of Claim 11 wherein said semiconductor substrate comprises. silicon and the step of forming a first electrically conductive layer comprises forming a layer of metal on said silicon and annealing said device at a temperature at which said metal forms a silicide with said silicon.
Claim 15
Dependent Claim
26 words
The method of Claim 11 wherein the step of forming said first electrically conductive layer comprises forming said layer by selective chemical vapor deposition of metal.
Claim 16
Dependent Claim
21 words
The method of Claim 11 wherein said second insulating layer is selectively removed by the application thereto of a directional etchant.
Claim 17
Dependent Claim
22 words
The method of Claim 14 wherein said directional etchant comprises a radio frequency plasma of tetrafluoromethane and hydrogen or trifluoromethane and helium.
Claim 18
Dependent Claim
64 words
The method of Claim 14 wherein: said first electrically conductive layer covers the exposed surfaces of said semiconductor device between said retained portions of said second insulating layer; and further comprising the step of: forming a second electrically conductive layer over the exposed surfaces of said first electrically conductive layer, said first insulating layer portions, and said retained portions of said second insulating layer.
Claim 19
Dependent Claim
38 words
The method of Claim 16 wherein: said base, emitter and drift regions each comprise silicon semiconductor material; said first insulating layer comprises silicon nitride or silicon dioxide; and said second insulating layer comprises silicon nitride or silicon dioxide.
Claim 20
Dependent Claim
31 words
The method of Claim 11 and further including the step of: introducing dopant impurities of said second conductivity type below the surfaces of said semiconductor device exposed by said etching step.
Claim 21
Dependent Claim
47 words
The method of Claim 18 wherein said semiconductor substrate comprises silicon and the step of forming said first electrically conductive layer comprises forming a layer of metal on said silicon and annealing said device at a temperature at which said metal forms a silicide with said silicon.
Claim 22
Dependent Claim
26 words
The method of Claim 18 wherein the step of forming said first electrically conductive layer comprises forming said layer by selective chemical vapor deposition of metal.
Claim 23
Dependent Claim
21 words
The method of Claim 18 wherein said second insulating layer is selectively removed by the application thereto of a directional etchant.
Claim 24
Dependent Claim
22 words
The method of Claim 21 wherein said directional etchant comprises a radio frequency plasma of tetrafluoromethane and hydrogen or trifluoromethane and helium.
Claim 25
Dependent Claim
64 words
The method of Claim 21 wherein: said first electrically conductive layer covers the exposed surfaces of said semiconductor device between said retained portions of said second insulating layer; and further comprising the step of forming a second electrically conductive layer over the exposed surfaces of said first electrically conductive layer, said first insulating layer portions, and said retained portions of said second insulating layer.
Claim 26
Dependent Claim
38 words
The method of Claim 23 wherein: said base, emitter and drift regions each comprise silicon semiconductor material; said first insulating layer comprises silicon nitride or silicon dioxide; and said second insulating layer comprises silicon nitride or silicon dioxide.
Claim 27
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 16.
Claim 28
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 17.
Claim 29
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 18.
Claim 30
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 23.
Claim 31
Dependent Claim
15 words
The semiconductor device including an electrical short circuit formed by the method of Claim 24.
References Cited (Backward Citations)
No citation records indexed.
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