Method and circuit for suppressing sequential "zeroes" data

Claim 3

A circuit for suppressing sequential "zeroes" data comprising: the transmitting portion (1) and the receiving portion (2), said transmitting portion (1) having a selector (12), first memory (13), second memory (14), sequential zeroes detecting circuit (15) and multiplexer (16), said first memory (13), second memory (14) and sequential zeroes detecting circuit (15) being arranged between said selector (12) and said multiplexer (16), so as to input a frame through said selector exchanged on a data generator (11) for generating said frame, when said sequential zeroes detecting circuit (15) detects sequential zeroes in said frame, said circuit (15) reading out said frame from said second memory (14) and causing said multiplexer 16 to insert the datum "1" in said frame, reading out the portion of said frame forced out by said insertion of said datum "1" from said first memory (13) with exchange of said selector (12) from said data generator (11) toward said first memory (13), adding said forced out portion to the top of the next frame to said frame through said selector 12, said receiving portion (2) having a flip flop (21), inserted "1" detecting circuit (22), clock generator (23), when said inserted "I" detecting circuit (22) detects said datum "1" in a frame sent from said transmitting portion (1), said circuit (22) preventing said clock generator (23) from sending clock pulses to said flip flop (21), whereby said datum "1" is not output from said frame received in said flip flop (21).

Claim 4

A circuit for suppressing sequential "zeroes" data comprising: the transmitting portion (1) and the receiving portion (2), said transmitting portion (1) having a selector (12), first memory (13), second memory (14), sequential zeroes detecting circuit (15) and multiplexer (16), said first memory (13), second memory (14) and sequential zeroes detecting circuit (15) being arranged between said selector (12) and said multiplexer (16), so as to input a frame through said selector exchanged on a data generator (11) for generating said frame, when said sequential zeroes detecting circuit (15) detects sequential zeroes in said frame, said circuit (15) reading out said frame from said second memory (14) and causing said multiplexer 16 to insert the datum "1" in said frame, reading out the portion of said frame forced out by said insertion of said datum "1" from said first memory (13) with exchange of said selector (12) from said data generator (11) toward said first memory (13), adding said forced out portion to the top of the next frame to said frame through said selector 12, said receiving portion (2) having a flip flop (21), inserted "1" detecting circuit (22), clock generator (23), when said inserted "I" detecting circuit (22) detects said datum "1" in a frame sent from said transmitting portion (1), said circuit (22) preventing said clock generator (23) from sending clock pulses to said flip flop (21), whereby said datum "1" is not output from said frame received in said flip flop (21).

Claim 5

A circuit for suppressing sequential "zeroes" data according to claim 1, wherein said second memory (14) of said transmitting portion (1) comprises buffer memories(141 and 142)which write and read alternatively, said inserted "I" detecting circuit (22) of said receiving portion (2) comprises a counter (222) which stops said clock generator 23 in the case of detecting said datum "I" in said frame sent from said transmitting portion (1).