Patent EP0201245A2 successfully refreshed from Google Patents.
EP0201245A2
Expired / Lapsed
EP
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Interlace to non-interlace scan converter for RGB format video input signals
Assignee: RCA Licensing Corp
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Filing: 1986-04-24
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Granted: —
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Expires: 2006-04-24
Abstract
Abstract A speed-up memory (22,24,26), converts interlaced RGB input signals to double line-rate - (progressive scan) form. A vertical detail signal (S3) is derived from the RGB input signals before or after speed-up and a vertical peaking signal (S4) is derived from the detail signal. During the first read . operation of the speed-up memory both signals (S3,S4) are added (84,86 with 32,42,52) to the speeded-up signals to effect a preshoot of the resultant signal, and during the second speed-up memory read operation only the peaking signal (S4) is added (32,42,52) to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.
Inventors
- 👤 Donald Henry Willis
- 👤 Russell Thomas Fling
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:55
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/14; H04N9/00; H04N9/64; H04N9/646; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
177 words
Interlaced to non-interlaced scan conversion apparatus, comprising: input means (10,12,14) for receiving first, second and third color component signals (R,G,B) representative of an image raster scanned in interlaced fashion at a given horizontal line rate; and video speed-up circuit means (22,24,26), coupled to said input means, for providing first, second and third double line rate color component video ouput signals (R',G',B'); characterized by vertical detail signal forming means (70,80), coupled to said input means or said speed-up circuit means, for providing a double line-rate vertical detail representative signal (S3); processing means (82), coupled to said vertical detail signal forming means, for providing a double !ine rate vertical peaking signal (S4); and output means (84.86,88), having a first operative condition for combining said vertical peaking and detail signals (S3,S4) with every other line of said double line-rate video output signals for causing these lines to exhibit preshoot and having a second operative condition for combining said vertical peaking signal (S4) with intermediate lines of said double line-rate video output signals for causing the intermediate lines to exhibit overshoot.
Claim 2
Dependent Claim
177 words
Interlaced to non-interlaced scan conversion apparatus, comprising: input means (10,12,14) for receiving first, second and third color component signals (R,G,B) representative of an image raster scanned in interlaced fashion at a given horizontal line rate; and video speed-up circuit means (22,24,26), coupled to said input means, for providing first, second and third double line rate color component video ouput signals (R',G',B'); characterized by vertical detail signal forming means (70,80), coupled to said input means or said speed-up circuit means, for providing a double line-rate vertical detail representative signal (S3); processing means (82), coupled to said vertical detail signal forming means, for providing a double !ine rate vertical peaking signal (S4); and output means (84.86,88), having a first operative condition for combining said vertical peaking and detail signals (S3,S4) with every other line of said double line-rate video output signals for causing these lines to exhibit preshoot and having a second operative condition for combining said vertical peaking signal (S4) with intermediate lines of said double line-rate video output signals for causing the intermediate lines to exhibit overshoot.
Claim 3
Dependent Claim
99 words
Apparatus as recited in Claim 1 wherein said video speed-up circuit means comprises memory means (22,24,26) having a write mode for storing each line of said color component signals and having first and second read modes for recovering each stored line twice thereby doubling the line rate of the stored signals and wherein said output means includes circuit means (88) for placing said output means in said first operative condition during said first read mode of said memory means and for placing said output means in said second operative condition during said second read mode of said memory means.
Claim 4
Dependent Claim
62 words
Apparatus as recited in Claim 1 or 2 wherein said vertical detail signal forming means comprises: comb filter means (70) coupled to said matrix means for forming a vertical detail representative signal (S2) at said given line rate; and further video speed up circuit means (80) coupled to said comb filter means for providing said double line-rate vertical detail representative signal (S3).
Claim 5
Dependent Claim
61 words
Apparatus as recited in Claim 1 or 2 wherein said vertical detail signal forming means comprises: matrix means (60 Fig. 3) coupled to said video speed-up circuit means (22,24,26) for providing a luminance representative signal at double said given line rate; and comb filter means (70') coupled to said matrix means for forming said double line-rate vertical detail representative signal (S3).
Claim 6
Dependent Claim
73 words
Apparatus as recited in Claim 3 or 4 wherein said comb filter means comprises delay means (72 Fig. 4) having an input and an output, switch means (73) for selectively connecting said input of said delay means (72) to said output thereof and to said matrix means (60) and subtractor means (74) having a first input connected to said matrix means and a second input connected to said output of said delay means.
Claim 7
Dependent Claim
71 words
Apparatus as recited in any preceding Claim wherein said output means comprises: first means (84) for adding said vertical peaking and detail signals (S3,S4) to form a sum signal (S5); and circuit means for subtracting (86 with 32,42,52) said sum signal from said every other line of said double line-rate video output signals and for adding (32,42,52) said peaking signal to said intermediate lines of said double line-rate video output signals.
Claim 8
Dependent Claim
77 words
Apparatus as recited in Claim 6 wherein said circuit means comprises: first, second and third adder means (32,42,52), each having a first input for receiving a respective one of said double line-rate video output signals and having a second input; inverter means (86) for inverting said sum signal; and switch means for selectively coupling said second inputs of said first, second and third adder means - (32,42,52) to said inverter means and to said processing means (82)
References Cited (Backward Citations)
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